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参数资料
| 型号： | 5962R9855201VYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 36/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962R9855201VYC |
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41
Output Enable Instruction Memory. This signal
allows memory to place data on the instruction data bus.
The Store Register to Instruction Memory (STRI)
instruction removes OE during the CK2 internal clock
cycle. OE enters a high-impedance state when the
UT69R000 is in the test mode (TEST = 0).
OPERAND DATA BUS CONTROL
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
116
B2
TTO
Data Strobe. Indicates valid data is on the Operand Data
bus. The UT69R000 places DS in a high-impedance state
when it does not control the Operand buses.
42
R12
TTO
INSTRUCTION MEMORY CONTROL
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
43
R13
TTO
Write Enable Memory. This signal allows the
UT69R000 to write to instruction memory. The Store
Register to Instruction Memory (STRI) instruction
asserts WE during the CK2 internal clock cycle. WE
enters a high-impedance state when the UT69R000 is in
the test mode (TEST = 0).
AL
Continued from page 40.
AL
UART CONTROL/TIMER CLOCK
UARTIN
127
F1
TUI
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
UARTOUT
128
G1
TTO
AH
UART Input. The UT69R000 receives serial data
through this input. The serial data is stored in the
UT69R000’s Receiver Buffer Register (RCVR). It is
tied to an internal pull-up resistor.
UART Output. The serial data stored in the UT69R000’s
Transmitter Buffer Register (TXMT) is transmitted
through this output. The UART output is fixed at 9600
baud, with eight data bits, odd-parity, and one stop bit.
UARTOUT enters a high-impedance state when the
UT69R000 is in the test mode ( TEST=0). (9600 baud @
TIMCLK = 12 MHz)
Continued on page 42.
WE
OE
DS
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| 5962R9863701VGA | 制造商:Analog Devices 功能描述:- Rail/Tube |
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