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参数资料
| 型号： | 5962R9855201VYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 37/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962R9855201VYC |
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42
Test (Input). Asserting this input places the UT69R000
into a test mode. In this mode, all the UT69R000’s
outputs, except OSCOUT and SYSCLK, enter a high-
impedance state. When using TEST, the UT69R000
must have a MRST. MRST must be held active for at
least one SYSCLK period after TEST is deasserted to
assure proper operation (see figure 41b). TEST is tied
to an internal pull-up resistor.
TIMCLK
53
L13
TI
UART CONTROL/TIMER CLOCK
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
DI2
48
N12
TDI
Timer Clock. This 12 MHz clock input generates the baud
rate for the UT69R000’s internal UART. The input also
provides the clock for the UT69R000’s two internal timers
(TIMER A and TIMER B).
Discrete Input 2. Asserting this input sets bit 3 in the
System Status Register Bit 3 is read with the Input Register
Instruction (INR). Tied to an internal pull-down resistor.
(asynchronous input).
TEST
46
P13
TUI
DI1
49
N13
TDI
--
Discrete Input 1. Asserting this input sets bit 8 in the
System Status Register. Bit 8 is read with the Input
Register Instruction (INR). Tie to a internal pull-down
resistor. (asynschronous input).
--
Continued from page 41
AL
PROCESSOR MODE
OD0
104
B7
TTO
PIN NAME
PIN NUMBER
FLTPK
PGA
TYPE
ACTIVE
DESCRIPTION
OD4
108
A4
--
Output Discrete Bus (OD(7:0)). These outputs reflect
the status of bits 0 through 7 of the Status/Output
Discrete Register. Write to this register using Output
Register Instruction (OTR). Outputs enter a high-
impedance state when the UT69R000 is placed in the
test mode (TEST = 0).
OD1
OD2
OD3
105
106
107
B6
C6
A5
OD5
OD6
OD7
109
110
111
A3
B4
C5
--
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