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参数资料
型号： 5V19EE904NLGI
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟及定时
英文描述： 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封装： 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件页数： 15/29页
文件大小： 292K
代理商： 5V19EE904NLGI
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
22
IDT5V19EE904
REV H 042211
0x22
10
CZ1_CFG4
IP1[2:0]_CFG4
RZ1[3:0]_CFG4
PLL1 Loop Parameter
0x23
10
CZ1_CFG5
IP1[2:0]_CFG5
RZ1[3:0]_CFG5
0x24
10
CZ1_CFG0
IP1[2:0]_CFG0
RZ1[3:0]_CFG0
0x25
10
CZ1_CFG1
IP1[2:0]_CFG1
RZ1[3:0]_CFG1
0x26
10
CZ1_CFG2
IP1[2:0]_CFG2
RZ1[3:0]_CFG2
0x27
10
CZ1_CFG3
IP1[2:0]_CFG3
RZ1[3:0]_CFG3
0x28
00
Reserved
D1[6:0]_CFG0
PLL1 input divider and input sel
D1[6:0] - 127 step Ref Div
D1 = 0 means power down.
0x29
00
Reserved
D1[6:0]_CFG1
0x2A
00
Reserved
D1[6:0]_CFG2
0x2B
00
Reserved
D1[6:0]_CFG3
0x2C
00
Reserved
D1[6:0]_CFG4
0x2D
00
Reserved
D1[6:0]_CFG5
0x2E
01
N1[7:0]_CFG4
N - Feedback Divider
2 - 4095 (value of “0” is not
allowed) Total feedback with A,
using provided calculation
0x2F
01
N1[7:0]_CFG5
0x30
01
N1[7:0]_CFG0
0x31
01
N1[7:0]_CFG1
0x32
01
N1[7:0]_CFG2
0x33
01
N1[7:0]_CFG3
0x34
00
N3[11:8]_CFG0
N1[11:8]_CFG0
PLL3 Feedback Divider
0x35
00
N3[11:8]_CFG1
N1[11:8]_CFG1
0x36
00
N3[11:8]_CFG2
N1[11:8]_CFG2
0x37
00
N3[11:8]_CFG3
N1[11:8]_CFG3
0x38
00
N3[11:8]_CFG4
N1[11:8]_CFG4
0x39
00
N3[11:8]_CFG5
N1[11:8]_CFG5
0x3A
00
CZ2_CFG4
IP2[2:0]_CFG4
RZ2[3:0]_CFG4
PLL2 Loop Parameter
0x3B
00
CZ2_CFG5
IP2[2:0]_CFG5
RZ2[3:0]_CFG5
0x3C
00
CZ2_CFG0
IP2[2:0]_CFG0
RZ2[3:0]_CFG0
0x3D
00
CZ2_CFG1
IP2[2:0]_CFG1
RZ2[3:0]_CFG1
0x3E
00
CZ2_CFG2
IP2[2:0]_CFG2
RZ2[3:0]_CFG2
0x3F
00
CZ2_CFG3
IP2[2:0]_CFG3
RZ2[3:0]_CFG3
0x40
00
Reserved
D2[6:0]_CFG0
PLL2 Reference Divide and Input
Select
D2[6:0] - 127 step Ref Div
D2 = 0 means power down.
0x41
00
Reserved
D2[6:0]_CFG1
0x42
00
Reserved
D2[6:0]_CFG2
0x43
00
Reserved
D2[6:0]_CFG3
0x44
00
Reserved
D2[6:0]_CFG4
0x45
00
Reserved
D2[6:0]_CFG5
0x46
01
N2[7:0]_CFG4
N2[7:0] - PLL2 Feedback Divider
2 - 4095 (value of “0” is not
allowed).
(See Addr 0x4C:0x51 for
N2[15:8])
0x47
01
N2[7:0]_CFG5
0x48
01
N2[7:0]_CFG0
0x49
01
N2[7:0]_CFG1
0x4A
01
N2[7:0]_CFG2
0x4B
01
N2[7:0]_CFG3
0x4C
80
SSENB_CFG0
0
IP3[4]_CFG0
N2[11:8]_CFG0
N2[11:8] - PLL2 Feedback Divide
PLL3 Spread Spectrum
SSENB - Spread Spectrum
Enable
SSENB = 1 means ON
IP3[4:0] - PLL3 Charge Pump
Current.
0x4D
80
SSENB_CFG1
0
IP3[4]_CFG1
N2[11:8]_CFG1
0x4E
80
SSENB_CFG2
0
IP3[4]_CFG2
N2[11:8]_CFG2
0x4F
80
SSENB_CFG3
0
IP3[4]_CFG3
N2[11:8]_CFG3
0x50
80
SSENB_CFG4
0
IP3[4]_CFG4
N2[11:8]_CFG4
0x51
80
SSENB_CFG5
0
IP3[4]_CFG5
N2[11:8]_CFG5
0x52
00
Reserved
0x53
00
Reserved
0x54
00
Reserved
Addr
Default
Register
Hex
Value
Bit #
Description
76
5
4
3
2
1
0
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