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| 型号： | 5V19EE904NLGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封装： | 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32 |
| 文件页数： | 2/29页 |
| 文件大小： | 292K |
| 代理商： | 5V19EE904NLGI |
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IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
10
IDT5V19EE904
REV H 042211
Spread Spectrum Generation (PLL3)
PLL3 support spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The technique is different from
that used in PLL0. The programmable spread spectrum
generation parameters are SS_D3[7:0], SSVCO[15:0],
SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the
memory address range of 0x4C to 0x85 for PLL3. The
spread spectrum generation on PLL3 can be
enabled/disabled using the SSENB bit. To enable spread
spectrum, set SSENB = '1'.
For Spread Enabled:
Spread spectrum is configured using SS_D3(spread
spectrum reference divide)
and SSVCO (spread spectrum loop feedback counter).
SS is the total Spread Spectrum amount (I.e. center spread
+0.5% has a total spread of 1.0% and down spread -0.5%
has a total spread of 0.5%.)
Loop Filter
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low-jitter
frequency generation. The specific loop filter components
that can be programmed are the resistor via the RZ[3:0] bits,
zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and
the charge pump current via the IP[2:0] bits (for PLL0, PLL1
and PLL2) or IP[3:0] (for PLL3).
The following equations govern how the loop filter is set for
PLL0 - PLL2:
Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0
kOhm
Zero capacitor (Cz) = 196 pF + CZ* 217 pF
Pole capacitor (Cp) = 15 pF
Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA
VCO gain (KVCO) = 900 MHz/V * 2
π
The following equations govern how the loop filter is set for
PLL3:
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
Zero capacitor (Cz) = 250 pF
Pole capacitor (Cp) = 15 pF
For Non-Spread Spectrum Operation:
For Spread Spectrum Operation:
VCO gain (KVCO) = 900 MHz/V * 2
π
=
SS_D3
(Eq. 10)
F
IN
4 * F
MOD
SSVCO =
F
VCO
F
MOD
[0.5 *
*
(Eq. 11)
( 1 + SS/400) + 5]
Resistor(Rz)=
(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
* RZ[0] + 6*(1 – RZ[0])
kOhms (Eq. 12)
Resistor(Rz)=
(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))
* RZ[0] + 6*(1 – RZ[0])
kOhms (Eq. 13)
Charge
pump(Ip)
=
24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
A (Eq. 14)
3+(5* IP[3]) +(11* IP[4])
Charge
pump(Ip)
=
12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))
A (Eq. 14)
27+(5* IP[3]) +(11* IP[4])
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5V19EE904NLGI8 | 功能描述:时钟发生器及支持产品 EEPROM PROGRAMMABLE PLL AND VCXO RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 5V1A-ADAPTER | 制造商:Distributed By MCM 功能描述:5V 1A Switching AC Power Supply - Micro USB |
| 5V1A-USB | 制造商:Gravitech 功能描述:USB WALL ADAPTER 5V 1A |
| 5V1BC | 制造商:SEMTECH_ELEC 制造商全称:SEMTECH ELECTRONICS LTD. 功能描述:Silicon Epitaxial Planar Zener Diodes |
| 5V1BCA | 制造商:SEMTECH_ELEC 制造商全称:SEMTECH ELECTRONICS LTD. 功能描述:Silicon Epitaxial Planar Zener Diodes |
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