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参数资料
| 型号： | 5V19EE904NLGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32 |
| 封装： | 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32 |
| 文件页数： | 3/29页 |
| 文件大小： | 292K |
| 代理商： | 5V19EE904NLGI |
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IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
11
IDT5V19EE904
REV H 042211
PLL Loop Bandwidth:
Charge pump gain (K
φ) = Ip / 2π
VCO gain (KVCO) = 900 MHz/V * 2
π
M = Total multiplier value (See the Reference Divider,
Feedback Divider and Output Divider section for more
detail)
ωc = (Rz * Kφ * KVCO * Cz)/(M * (Cz + Cp))
Fc =
ωc / 2π
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce the phase margin thus
compromising loop stability.
To determine if the loop is stable, the phase margin (
φm)
needs to be calculated as follows.
Phase Margin:
ωz = 1 / (Rz * Cz)
ωp = (Cz + Cp)/(Rz * Cz * Cp)
φm = (360 / 2π) * [tan-1(ωc/ ωz) - tan-1(ωc/ ωp)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 5V19EE904NLGI8 | 功能描述:时钟发生器及支持产品 EEPROM PROGRAMMABLE PLL AND VCXO RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| 5V1A-ADAPTER | 制造商:Distributed By MCM 功能描述:5V 1A Switching AC Power Supply - Micro USB |
| 5V1A-USB | 制造商:Gravitech 功能描述:USB WALL ADAPTER 5V 1A |
| 5V1BC | 制造商:SEMTECH_ELEC 制造商全称:SEMTECH ELECTRONICS LTD. 功能描述:Silicon Epitaxial Planar Zener Diodes |
| 5V1BCA | 制造商:SEMTECH_ELEC 制造商全称:SEMTECH ELECTRONICS LTD. 功能描述:Silicon Epitaxial Planar Zener Diodes |
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