参数资料
型号: 5V19EE904NLGI
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封装: 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件页数: 4/29页
文件大小: 292K
代理商: 5V19EE904NLGI
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
12
IDT5V19EE904
REV H 042211
SEL[2:0] Function
The IDT5V19EE904 can support up to six unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[2:0]
pins. Alternatively, users may use I2C interface to configure
these registers on-the-fly.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to
be either active HIGH or LOW with the SP bit (0x02). When
SP is “0” (default), the pin becomes active HIGH and when
SP is “1”, the pin becomes active LOW. The SD/OE pin can
be configured as either to shutdown the PLLs or to
enable/disable the outputs.
1 Assert to disable the outputs whose OE bits are set
2 Assert to shut down power, on the outputs and 3-level pins
Configuration OUTx IO Standard
Users can configure the individual output IO standard from
a specified 1.8 to 3.3V power supplies. Each output can
support 1.8 to 3.3V LVTTL. OUT0 can only be a 3.3V
single-ended output.
Programming the Device
I2C may be used to program the IDT5V19EE904.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5V19EE904 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
The frame formats are shown in the following illustration.
Framing
SEL2
SEL1
SEL0
Configuration Selections
0
Select CONFIG0
0
1
Select CONFIG1
0
1
0
Select CONFIG2
0
1
Select CONFIG3
1
0
Select CONFIG4
1
0
1
Select CONFIG5
1
0
Reserved (Do not use)
1
Reserved (Do not use)
SD/O E
OE M o d e
1
S D M ode
2
SH
SP
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