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参数资料
| 型号： | 70T3399S133BCGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256 |
| 文件页数： | 16/28页 |
| 文件大小： | 327K |
| 代理商： | 70T3399S133BCGI8 |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
23
Functional Description
TheIDT70T3339/19/99providesatruesynchronousDual-PortStatic
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
A HIGH on
CE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70T3339/19/99s for depth
expansion configurations. Two cycles are required with
CE0 LOW and
CE1 HIGHto re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as
CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location 7FFFE when
CEL = VIL and R/WL= VIH. Likewise, the
right port interrupt flag (
INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag (
INTR),therightportmustreadthememorylocation7FFFF(3FFFF
or 3FFFE for IDT70T3319 and 1FFFF or 1FFFE for IDT70T3399). The
message (18 bits) at 7FFFE or 7FFFF (3FFFF or 3FFFE for IDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressable SRAM location. If the interrupt function is not used, address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
partoftherandomaccessmemory.RefertoTruthTableIII fortheinterrupt
operation.
Collision Detection
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulled low. When ZZ is pulled high, the port will enter sleep mode where
it will meet lowest possible power conditions. The sleep mode timing
diagramshowsthemodes ofoperation:NormalOperation,NoRead/Write
Allowed and Sleep Mode.
For normal operation all inputs must meet setup and hold times prior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/
Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
of valid data.
During sleep mode the RAM automatically deselects itself. The RAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
without impacting the RAMs sleep current (IZZ).All outputs will remain in
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
Collision is defined as an overlap in access between the two ports
resulting in the potential for either reading or writing incorrect data to a
specific address. For the specific cases: (a) Both ports reading - no
data is corrupted, lost, or incorrectly output, so no collision flag is output
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capture data that is in a state of transition and hence the reading port’s
collision flag is output. (c) Both ports writing - there is a risk that the two
ports will interfere with each other, and the data stored in memory will
not be a valid write from either port (it may essentially be a random
combination of the two). Therefore, the collision flag is output on both
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (
COL
X) is asserted on the 2nd or 3rd rising clock
edge of the affected port following the collision, and remains low for
one cycle. Please refer to Collision DetectionTiming table on Page 21.
During that next cycle, the internal arbitration is engaged in resetting
the alert flag (this avoids a specific requirement on the part of the user
to reset the alert flag). If two collisions occur on subsequent clock
cycles, the second collision may not generate the appropriate alert
Collision detection on the IDT70T3339/19/99 represents a
significant advance in functionality over current sync multi-ports, which
have no such capability. In addition to this functionality the
IDT70T3339/19/99 sustains the key features of bandwidth and
flexibility. The collision detection function is very useful in the case of
bursting data, or a string of accesses made to sequential addresses, in
that it indicates a problem within the burst, giving the user the option of
either repeating the burst or continuing to watch the alert flag to see
whether the number of collisions increases above an acceptable
threshold value. Offering this function on chip also allows users to
reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s. This reduces board space and design complexity, and gives
the user more flexibility in developing a solution.
flag. A third collision will generate the alert flag as appropriate. In the
event that a user initiates a burst access on both ports with the same
starting address on both ports and one or both ports writing during
each access (i.e., imposes a long string of collisions on contiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle. Please refer to the Collision Detection timing waveform on page
21.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 70T3399S133BCI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Rail/Tube |
| 70T3399S133BCI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Tape and Reel |
| 70T3399S133BF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
| 70T3399S133BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Tape and Reel |
| 70T3399S133BFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
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