参数资料
型号: 70T3399S133BCGI8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: SRAM
英文描述: 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256
封装: 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
文件页数: 9/28页
文件大小: 327K
代理商: 70T3399S133BCGI8
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
17
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
TimingWaveform of Flow-ThroughRead-to-Write-to-Read(OEControlled)(2)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
5652 drw 13
Qn
DATAOUT
CE1
UB, LB
tCD1
Qn + 1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
tCKHZ
Qn + 3
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
NOP
READ
tCKLZ
(3)
(1)
tSW tHW
WRITE
(4)
,
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
(3)
DATAIN
Dn + 2
CE0
CLK
5652 drw 14
Qn
DATAOUT
CE1
UB, LB
tCD1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
Qn + 4
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
WRITE
READ
tCKLZ
(1)
Dn + 3
tOHZ
tSW tHW
OE
tOE
,
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