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参数资料
| 型号： | 70T3399S133BCGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256 |
| 文件页数： | 26/28页 |
| 文件大小： | 327K |
| 代理商： | 70T3399S133BCGI8 |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
7
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2.
ADS, CNTEN, REPEAT = VIH.
3.
OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table I—Read/Write and Enable Control (1,2,3,4)
Truth Table II—Address Counter Control (1,2)
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/
W, CE0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.
ADS and REPEAT are independent of all other memory control signals including CE0, CE1, UB and LB.
5. The address counter advances if
CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB and LB.
6. When
REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via
ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
OE
CLK
CE0
CE1
UB
LB
R/
W
ZZ
Upper Byte
I/O9-17
Lower Byte
I/O0-8
MODE
X
↑
H
X
L
High-Z
Deselected–Power Down
X
↑
X
L
X
L
High-Z
Deselected–Power Down
X
↑
L
H
X
L
High-Z
Both Bytes Deselected
X
↑
LH
H
L
High-Z
DIN
Write to Lower Byte Only
X
↑
LH
L
DIN
High-Z
Write to Upper Byte Only
X
↑
L
H
LL
DIN
Write to Both Bytes
L
↑
L
H
HL
High-Z
DOUT
Read Lower Byte Only
L
↑
LH
H
L
DOUT
High-Z
Read Upper Byte Only
L
↑
LH
L
H
L
DOUT
Read Both Bytes
H
↑
L
H
L
X
L
High-Z
Outputs Disabled
X
H
High-Z
Sleep Mode
5652 tbl 02
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
REPEAT(6)
I/O(3)
MODE
An
X
An
↑
L(4)
XH
DI/O (n)
External Address Used
XAn
An + 1
↑
H
L(5)
HDI/O(n+1)
Counter Enabled—Internal Address generation
X
An + 1
↑
HH
H
DI/O(n+1)
External Address Blocked—Counter disabled (An + 1 reused)
XX
An
↑
XX
L(4)
DI/O(n)
Counter Set to last valid
ADS load
5652 tbl 03
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相关代理商/技术参数 |
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| 70T3399S133BCI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Rail/Tube |
| 70T3399S133BCI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Tape and Reel |
| 70T3399S133BF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
| 70T3399S133BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Tape and Reel |
| 70T3399S133BFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
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