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参数资料
| 型号： | 70T3399S133BCGI8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256 |
| 封装： | 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256 |
| 文件页数： | 7/28页 |
| 文件大小： | 327K |
| 代理商： | 70T3399S133BCGI8 |
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6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
15
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
NOTES:
1.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
CLK"A"
R/
W"A
"
ADDRESS"A"
DATAIN"A"
CLK"B"
R/
W"B"
ADDRESS"B"
DATAOUT"B"
tSW
tHW
tSA
tHA
tSD
tHD
tSW
tHW
tSA
tHA
tCO(3)
tCD2
NO
MATCH
VALID
NO
MATC
H
MATC
H
MATC
H
VALID
5652 drw 09
tDC
,
DATAIN "A"
CLK "B"
R/
W "B"
ADDRESS "A"
R/
W "A"
CLK "A"
ADDRESS "B"
NO
MATCH
NO
MATCH
VALID
tCD1
tDC
DATAOUT "B"
5652 drw 10
VALID
tSW
tHW
tSA
tHA
tSD
tHD
tHW
tCD1
tCO
tDC
tSA
tSW
tHA
(3)
,
NOTES:
1.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2.
OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 70T3399S133BCI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Rail/Tube |
| 70T3399S133BCI8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Tape and Reel |
| 70T3399S133BF | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
| 70T3399S133BF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Tape and Reel |
| 70T3399S133BFI | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube |
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