参数资料
型号: 71M6521BE-IGT/F
厂商: Maxim Integrated
文件页数: 39/97页
文件大小: 0K
描述: IC ENERGY METER 8K FLASH 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
系列: Single Converter Technology®
测量误差: 0.4%
电源电压: 3 V ~ 3.6 V
测量仪表类型: 单相,双相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
Internal
V3P3
WPULSE
2
OPT_TX
from OPT_TX UART
OPT_TXINV
A
OPT_TXMOD
EN
MOD
DUTY
DIO2
B
1
0
OPT_TXE[1:0]
OPT_FDC
2
OPT_TXMOD=1,
A
B
OPT_TXMOD=0
A
B
OPT_FDC=2 (25%)
1/38kHz
Figure 7: Optical Interface
Digital I/O
The device includes up to 14 pins of general purpose digital I/O. These pins are compatible with 5V inputs (no current-limiting
resistors are needed). Some are dual function that can alternatively be used as LCD drivers (DIO4-11, 14-17) and some share
functions with the optical port (DIO1, DIO2). On reset or power-up, all DIO pins are inputs until they are configured for the
desired direction under MPU control. The pins are configured by the DIO registers and by the five bits of the LCD_NUM
register (located in I/O RAM). Once declared as DIO, each pin can be configured independently as an input or output with the
DIO_DIRn bits. A 3-bit configuration word, DIO_Rx , can be used for certain pins, when configured as DIO, to individually assign
an internal resource such as an interrupt or a timer control. Table 53 lists the direction registers and configurability associated
with each group of DIO pins. Table 54 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register.
Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications
section and in the I/O RAM Description under LCD_NUM[4:0].
DIO
Pin number
PB
62
1
57
2
3
3
--
4
37
5
38
6
39
7
40
8
41
9
42
10
43
11
44
12
--
13
--
14
20
15
21
Data Register
Direction Register
0
0
1
1
2 -- 4 5
DIO0=P0 (SFR 0x80)
2 -- 4 5
DIO_DIR0 (SFR 0 xA2)
6
6
7
7
0
0
1
1
2 3 -- --
DIO1=P1 (SFR 0 x90)
2 3 -- --
DIO_DIR1 (SFR 0x91)
6
6
7
7
Internal Resources
Configurable
Y
Y
Y
--
Y
Y
Y
Y
Y
Y
Y
Y
--
--
--
--
DIO
Pin number
16
22
17
12
18
--
19
--
20
--
21
--
22
--
23
--
Data Register
Direction Register
0
0
1
1
-- -- -- --
DIO2=P2 (SFR 0xA0)
-- -- -- --
DIO_DIR2 (SFR 0 xA1)
--
--
--
--
Internal Resources
Configurable
N
N
--
--
--
--
--
--
Table 53: Data/Direction Registers and Internal Resources for DIO Pin Groups
V1.0
? 2005-2008 TERIDIAN Semiconductor Corporation
Page: 39 of 97
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