参数资料
型号: 71M6521BE-IGT/F
厂商: Maxim Integrated
文件页数: 77/97页
文件大小: 0K
描述: IC ENERGY METER 8K FLASH 64-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
系列: Single Converter Technology®
测量误差: 0.4%
电源电压: 3 V ~ 3.6 V
测量仪表类型: 单相,双相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
CE Calculations
The CE performs the precision computations necessary to accurately measure energy. These computations include offset
cancellation, products, product smoothing, product summation, frequency detection, and sag detection. All data computed by
the CE is dependent on the selected meter equation as given by EQU ( in I/O RAM ) . However, for the 6521BE CE code, EQU is
always 0.
EQU
Watt Formula
(WSUM)
W0SUM
Element Input Mapping
W1SUM I0SQSUM
I1SQSUM
0
VA IA (1 element, 2W 1 φ )
with tamper detection
VA*IA
VA*IB
IA
IB
CESTATUS
Since the CE_BUSY interrupt occurs at 2520.6Hz, it is desirable to minimize the computation required in the interrupt handler
of the MPU. The MPU can read the CE status word at every CE_BUSY interrupt.
CE
Address
0x11E8
Name
CESTATUS
Description
See description of CE status word below
The CE Status Word is used for generating early warnings to the MPU. It contains sag warnings for VA as well as the F0 bit, a
clock derived from the fundamental input frequency. CESTATUS provides information about the status of voltage and input AC
signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS
represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one
code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt.
The significance of the bits in CESTATUS is shown in the table below:
CESTATUS
[bit]
31-29
28
27
26
25
24-0
Name
Not Used
F0
CREEP
SAG_B
SAG_A
Not Used
Description
These unused bits will always be zero.
F0 is a square wave at the exact fundamental input frequency.
Mains Signal
F0
Normally zero. Becomes one when creep logic has been applied to either WA or WB.
Normally zero. These bits come one when the voltage in the respective channel remains
below SAG_THR for SAG_CNT samples. Will not return to zero until the voltage rises above
SAG_THR .
These unused bits will always be zero.
V1.0
? 2005-2008 TERIDIAN Semiconductor Corporation
Page: 77 of 97
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