参数资料
型号: 71M6533H-IGT/F
厂商: TERIDIAN SEMICONDUCTOR CORP
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP100
封装: LEAD FREE, LQFP-100
文件页数: 91/124页
文件大小: 2008K
代理商: 71M6533H-IGT/F
FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
69
3.8
Connecting Three-Wire EEPROMs
Wire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in Figure 35 and described below:
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6533/71M6534.
In order to prevent bus contention, a 10 k
to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with a resistor to prevent operation of the three-wire
device on power-up, before the 71M6533/71M6534 can establish a stable signal for CS and CLK.
The DIO_EEX register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4 and
DIO5 to Wire pins.
The -Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
Figure 35: Three-Wire EEPROM Connection
3.9
UART0 (TX/RX)
The UART0 RX pin should be pulled down by a 10 k
resistor and additionally protected by a 100 pF ce-
ramic capacitor, as shown in Figure 36.
Figure 36: Connections for UART0
TX
RX
71M6533/71M6534
10 k
Ω
100 pF
RX
TX
EEPROM
100 k
DIO4
DIO5
CLK
DI
V3P3D
100 k
CS
DIOn
DO
10 k
VCC
71M6533/71M6534
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