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参数资料
| 型号： | 71V25781YSA166BGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.5 ns, PBGA119 |
| 封装： | BGA-119 |
| 文件页数： | 6/22页 |
| 文件大小： | 627K |
| 代理商： | 71V25781YSA166BGI |
6.42
14
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
NOTES:
1.
Device
is
selected
through
entire
cycle;
CE
and
CS
1are
LOW,
CS
0is
HIGH.
2.
ZZ
input
is
LOW
and
LBO
is
Don't
Care
for
this
cycle.
3.
O1
(Ax)
represents
the
first
output
from
the
external
address
Ax.
I1
(Ay)
represents
the
first
input
from
the
external
addre
ss
Ay;
O1
(Az)
represents
the
first
output
from
the
external
address
Az;
O2
(Az)
represents
the
next
output
data
in
the
burst
sequence
of
the
base
address
Az,
etc.
where
A0
and
A1
are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
Timing Waveform of Combined Pipelined Read and Write Cycles(1,2,3)
C
L
K
A
D
S
P
A
D
R
E
S
G
W
A
D
V
O
E
D
A
T
A
O
U
T
tC
Y
C
tC
H
tC
L
tH
A
tS
W
tH
W
tC
L
Z
A
x
A
y
A
z
tH
S
I1
(A
y
)
tS
D
tH
D
tO
L
Z
tC
D
tC
D
C
D
A
TA
IN
(2
)
tO
E
O
1
(A
z
)
O
1
(A
z
)
S
in
g
le
R
e
a
d
P
ip
e
lin
e
d
B
u
rs
t
R
e
a
d
P
ip
e
lin
e
d
W
ri
te
O
1
(A
x
)
tO
H
Z
tS
S
tS
A
O
3
(A
z
)
O
2
(A
z
)
5
2
9
7
d
rw
0
9
tC
D
,
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