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参数资料
| 型号： | 72V293L6PFG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 64K X 18 OTHER FIFO, 4 ns, PQFP80 |
| 封装： | GREEN, PLASTIC, TQFP-80 |
| 文件页数： | 10/45页 |
| 文件大小： | 381K |
| 代理商： | 72V293L6PFG |
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18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN,LD,
or both together. When
REN and LD are restored to a LOW level, reading of
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmitsetupisinitiatedbyholding
RTLOWduringarisingRCLKedge.
RENandWEN mustbeHIGHbeforebringingRTLOW.Whenzerolatencyis
utilized,
REN doesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwo
words, but no more than D - 2 words should have been written into the FIFO,
and read from the FIFO, between Reset (Master or Partial) and the time of
Retransmit setup. If x18 Input or x18 Output bus Width is selected, D = 512 for
the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for
the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768
fortheIDT72V283and65,536fortheIDT72V293.Ifbothx9Inputandx9Output
bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the
IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for
the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and
131,072fortheIDT72V293.InFWFTmode,ifx18Inputorx18OutputbusWidth
is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for
the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263, 16,385
for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the
IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for
the IDT72V283 and 131,073 for the IDT72V293.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmitsetupbysetting
EFLOW.Thechangeinlevelwillonlybenoticeable
if
EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When
EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on
REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting
OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When
ORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
the first word appears on the outputs, no LOW on
RENisnecessary.Reading
all subsequent words requires a LOW on
REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
ForeitherIDTStandardmodeorFWFTmode,updatingofthe
PAE,HFand
PAF flags begin with the rising edge of RCLK that the RT is setup on. PAE is
synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafter
RTissetup,
the
PAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
that
RTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that
RT
is setup will update
PAF. RT is synchronized to RCLK.
TheRetransmitfunctionhastheoptionof2modesofoperation,either"normal
latency" or "zero latency". Figure 11 and Figure 12 mentioned previously,
relate to "normal latency". Figure 13 and Figure 14 show "zero latency"
retransmitoperation.Zerolatencybasicallymeansthatthefirstdatawordtobe
retransmitted,isplacedontotheoutputregisterwithrespecttotheRCLKpulse
thatinitiatedtheretransmit.
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| 7305-0-15-01-47-01-10-0 | BERYLLIUM COPPER, TIN LEAD (300) OVER NICKEL FINISH, PCB TERMINAL |
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相关代理商/技术参数 |
参数描述 |
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| 72V293L7-5BC | 功能描述:先进先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V293L7-5BCI | 功能描述:先进先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V293L7-5PF | 功能描述:先进先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V293L7-5PF8 | 功能描述:先进先出 128Kx9/ 64Kx18 3.3V SUPER SYNC II 先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72V293L7-5PF9 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin TQFP |
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