参数资料
型号: 73S1217F-EB-LITE
厂商: Maxim Integrated Products
文件页数: 90/93页
文件大小: 0K
描述: BOARD EVAL 73S1217F CBL/DOC/CD
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
73S12xxF Software User Guide
UG_12xxF_016
90
Rev. 1.50
4.5.1.3 VISA-1 Loopback Test
Teridian used the RFI Global test lab in the UK (listed on the www.emvco.com website) for VISA-1
testing. This lab used the VISA test suite for their EMV Level I qualification test services. Figure 14
shows the VISA-1 test flow which is specific to RFI’s test scripts. Source code for this test is also
included in the release.
Initialization
Enter Delay Time
(in Secs)
Power-Up Ok
(Good ATR)?
SELECT FILE
1PAY.SYS.DDF01
EMV Power
Down
M/m
Any other Key
Warm Reset OK?
Yes
No
APDU Exchange
No
Exchange OK?
End of Record?
or No Record?
Enter (M/m) Multi-
or (anykey) Single
Shot?
Delay Time Wait
EMV Power Up
Negotiable Mode?
No
PPS OK?
Yes
SingleShot?
Yes
No
Yes
No
Yes
READ RECORD
(00 B2 'P1' 0C 00)
Yes
P1 = 01
Increment RECORD
Index (P1)
Yes
No
Exchange OK?
Yes
No
Figure 14: VISA-1 Loopback Test Flow Chart
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