参数资料
型号: 73S8009R-IM/F
厂商: Maxim Integrated Products
文件页数: 7/23页
文件大小: 0K
描述: IC SMART CARD LEVEL SHIFT 20-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 490
应用: 智能卡读取器,写入器
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘
供应商设备封装: 20-QFN(4x4)
包装: 管件
DS_8009R_056
73S8009R Data Sheet
Pin
Name
I/OUC
Pin
(SO28)
5
Pin
(QFN20)
1
Type
I/O
Description
System controller data I/O to/from the card. Includes a pull-
up resistor to V DD.
AUX1UC
6
NA
I/O
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V DD.
AUX2UC
7
NA
I/O
System controller auxiliary data I/O to/from the card.
Includes a pull-up resistor to V DD.
CMDVCC%
CMDVCC#
8
9
2
3
I
I
Logic low on one or both of these pins will cause the LDO to
ramp the Vcc supply to the smart card and smart card
interface to the value described in the following table:
CMDVCC%
CMDVCC#
V CC Output Voltage
0
0
1.8 V
0
1
5.0 V
1
0
3.0 V
1
1
LDO off
Refer to for additional information on the CMDVCC% and
CMDVCC# operation.
RSTIN
RDY
10
12
4
6
I
O
Reset Input. This signal is the reset command to the card.
Signal to controller indicating the 73S8009R is ready
because V CC is above the required value after CMDVCC%
and/or CMDVCC# is asserted low. A 20 K Ω pull-up resistor
to V DD is provided internally. The pull-up is disabled in
PWRDN and CS=0 modes.
PWRDN
13
7
I
PWRDN=1 puts the circuit into low-power mode with all
analog functions disabled. The circuit will recover from the
PWRDN state in the same manner as recovery from a POR
event, taking approximately 1 ms. PWRDN assertion when
either CMDVCC% or CMDVCC# is low has no effect and is
ignored. There is no pull-up or pull-down provided on this pin.
Rev. 1.3
7
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