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参数资料
| 型号： | 7782 |
| 厂商： | 意法半导体 |
| 英文描述： | 32 Mbit (2Mb x 16, Dual Bank, Burst ) 1.8V Supply Flash Memory |
| 中文描述： | 32兆位（含2Mb × 16，双行，突发）1.8V电源快闪记忆体 |
| 文件页数： | 6/63页 |
| 文件大小： | 435K |
| 代理商： | 7782 |
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M58CR032C, M58CR032D
6/63
SUMMARY DESCRIPTION
The M58CR032 is a 32 Mbit (2Mbit x16) non-vola-
tile Flash memory that may be erased electrically
at block level and programmed in-system on a
Word-by-Word basis using a 1.65V to 2.0V V
DD
supply for the circuitry and a 1.65V to 3.3V V
DDQ
supply for the Input/Output pins. An optional 12V
V
PP
power supply is provided to speed up custom-
er programming. The V
PP
pin can also be used as
a control pin to provide absolute protection against
program or erase.
The device features an asymmetrical block archi-
tecture. M58CR032 has an array of 71 blocks and
is divided into two banks, Banks A and B, provid-
ing Dual Bank operations. While programming or
erasing in Bank A, read operations are possible in
Bank B or vice versa. Only one bank at a time is
allowed to be in program or erase mode. It is pos-
sible to perform burst reads that cross bank
boundaries. The bank architecture is summarized
in Table 2, and the memory maps are shown in
Figure 4. The Parameter Blocks are located at the
top of the memory address space for the
M58CR032C and at the bottom for the
M58CR032D.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory
array; at power-up the device is configured for
page mode read. In synchronous burst mode, data
is output on each clock cycle at frequencies of up
to 54MHz.
The M58CR032 features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
PP
≤
V
PPLK
all blocks are protected against
program or erase. All blocks are locked at Power
Up.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is di-
vided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 5, shows the Security Block and
Protection Register Memory Map.
The memory is offered in a TFBGA56, 0.75 mm
ball pitch package and is supplied with all the bits
erased (set to ’1’).
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