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| 型号： | 78Q8430EBST#DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 25/88页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 标准包装： | 1 |
| 系列： | * |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
31
Counter
Address
Counter Description
0x0B
Broadcast packets
0x0C
SQE errors
0x0D
Pause packets transmitted
0x0E
Transmitted bytes
0x0F
Received packets, 63 bytes or less
0x10
Received packets, 64 bytes
0x11
Received packets, 65 to 127 bytes
0x12
Received packets, 128 to 255 bytes
0x13
Received packets, 256 to 511 bytes
0x14
Received packets, 512 to 1023 bytes
0x15
Received packets, 1024 to 1518 (1522 for VLAN tag) bytes
0x16
Received packets, 1519 bytes or more (1523 or more for VLAN tag) bytes
0x17
CRC error and no alignment error
0x18
Alignment errors
0x19
Fragment errors (less than 64 bytes with CRC or alignment error)
0x1A
Jabbers (greater than 1518 or 1522 and CRC or alignment error)
0x1B
MAC errors
0x1C
Dropped packets
0x1D
Classification dropped packet
0x1E
Total received packets with no errors
0x1F
Total received multicast packets with no errors
0x20
Total received broadcast packets with no errors
0x21
Range errors (length field <= 1500 and received data <= 1500 and not control packet and
length field does not match data bytes received and unpadded packet and no
CRC/alignment errors
0x22
Out of range count (length field > 1500 and not control packet 8808)
0x23
Total received VLAN packets with no errors
0x24
Total received Pause packets with no errors
0x25
Total received Control packets with no errors
0x26
Total received bytes with no errors
0x27
Total received bytes with errors but not jabber nor fragment
6.6.2
Reading and Setting Counter Values
Before any counters can be accessed, the CCR value must be set appropriately. Bits 0 to 5 of the CCR
are the Address field. These bits must contain the address of the first counter to be accessed. Bit eight
of the CCR is the Access Mode bit. When the Access Mode bit is clear, the access mode is read. When
the Access Mode bit is set, the access mode is write. Bit nine of the CCR is the Clear on Read bit. The
Clear on Read bit is only relevant when the access mode is read. When the Clear on Read bit is set,
then the counter values are automatically reset to zero after the counter value is read. If a countable
event occurs at the same time as the reset, then the counter value is reset to one such that no countable
events are missed. Bit ten of the CCR must always be set.
the actual counter values. When the CCR Access Mode bit is cleared for read, only read access to the
CDR is allowed, and a read of the CDR will return the value of the counter specified by the CCR Address
field. When the CCR Access Mode bit is set to write, only write access to the CDR is allowed, and the
value written to the CDR will be written to the counter at the address specified by the CCR Address field.
allowing many counters to be accessed through repeated reads or writes on the CDR without the need to
reconfigure the CCR each time. When writing a value to a counter, if a countable event occurs at the
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