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| 型号： | 78Q8430EBST#DB |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 67/88页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 78Q8430 |
| 标准包装： | 1 |
| 系列： | * |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
7
1
Introduction
The Teridian 78Q8430 is a single chip 10Base-T/100Base-TX capable Fast Ethernet Media Access
Controller (MAC) and Physical Layer (PHY) transceiver. The device is optimized for video applications,
such as the Set Top Box (STB), and easily interfaces to available STB core processors, such as the
STi5100, STi5516, STi5514, ARM
and Intel based processors. The 78Q8430 is compliant with
applicable IEEE-802.3 standards. MAC and PHY configuration and status registers are provided as
specified by IEEE-802.3u.
The 78Q8430 operates over Category-5 Unshielded Twisted Pair (Cat-5 UTP) cabling in 100Base-TX
applications and over Cat-3 UTP in 10Base-T applications requiring only a dual 1:1 isolation transformer
interface to the copper media.
The Ethernet MAC section makes use of a 32 kB deep on-chip SRAM FIFO packet memory to adaptively buffer
transmit and receive data. SRAM memory can be dynamically allocated to either the transmit queues or the
receive queues as required to optimize throughput.
The host processor accesses the FIFO(s) using a simple asynchronous pseudo-SRAM like host bus interface.
A 32 bit wide bus is provided; the bus width can be pin-configured for 8-bit, 16-bit or 32-bit bus width at boot-up.
Big endian, little endian and mixed endian options are available in 32-bit operation; little endian is available for
16-bit operation. Different End-in variations are supported through internal circuitry with minimal user
intervention required.
The MAC interface logic may assert MEMWAIT during bus transactions, requesting wait states from the host
while critical internal data transfer completes. The MAC provides both half duplex and full duplex operation, as
well as support for full duplex flow control. Complete, portable device drivers for Linux
, OS20 and VxWorks
1.1
Systems Applications
are available.
The 78Q8430 operates from a single 3.3 V supply. Power down modes and power saving modes are
available. The 78Q8430 defaults to use an on-chip crystal oscillator. In this mode, a 25 MHz reference
crystal is connected between the XTLP and XTLN pins. Alternatively, an externally generated 25 MHz
clock can be connected to the XTLP pin. The chip will automatically configure itself to use the external
clock. In this mode of operation, a crystal is not required.
Figure 1 presents an overview of the 78Q8430 in a block diagram.
TERIDIAN
78Q8430
Single Chip
10/100 Ethernet
Controller
8-bit/16-bit/32-bit
System Bus
Configuration
EEPROM Interface
(Optional)
JTAG Interface
LED
Link (Programmable)
LED
Activity (Programmable)
RJ45
1:1
Transformer
CAT 5
Cable
Figure 1: 78Q8430 Block Diagram
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| 78Q8430STEM#DB | 功能描述:以太网开发工具 3-in-1 Silicon Delay Line RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
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