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参数资料
| 型号： | 935270523518 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64 |
| 文件页数： | 16/93页 |
| 文件大小： | 2118K |
| 代理商： | 935270523518 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
23 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
ATL buffer length = 400H, ITL buffer length = 200H.
This is insufcient use of the internal FIFO buffer RAM.
ATL buffer length = 1000H, ITL buffer length = 0H.
This will use the internal FIFO buffer RAM for only ATL transfers.
ATL buffer length = 0H, ITL buffer length = 800H.
This will use the internal FIFO buffer RAM for only ISO transfers.
The actual requirement for the buffer RAM need not reach the maximum size. You
can make your selection based on your application.
The following are some calculations of the ISO_A or ISO_B space for a frame of data:
maximum number of useful data sent during one USB frame is 1280 bytes (20 ISO
packets of 64 bytes). Total RAM size needed for this is 20
× 8 + 1280 = 1440 bytes.
Maximum number of packets for different endpoints sent during one USB frame is
150 (150 ISO packets of 1 byte). Total RAM size needed is:
150
× 8 + 150 × 1 = 1350 bytes.
The Ping buffer RAM (ITL0) and the Pong buffer RAM (ITL1) have a maximum size
of 2 kbytes each. All data needed for one frame can be stored in the Ping or the
Pong buffer RAM.
When the embedded system wants to initiate a transfer to the USB bus, the data
needed for one frame is transferred to the ATL buffer or the ITL buffer. The
microprocessor detects the buffer status through interrupt routines. When the
HcBufferStatus register (2CH - Read only) indicates that the buffer is empty, the
microprocessor can write data into the buffer. When the HcBufferStatus register
indicates that the buffer is full, that is, data is ready on the buffer, the microprocessor
needs to read data from the buffer.
For every 1 ms, there might be many events to generate interrupt requests to the
microprocessor for data transfer or status retrieval. However, each of the interrupt
types dened in this specication can be enabled or disabled by setting
Hc
PInterruptEnable register bits accordingly.
Fig 17. HC internal FIFO buffer RAM partitions.
MGT950
not used
ATL buffer
ITL0
top
bottom
ITL1
ISO_A
FIFO buffer RAM
ISO_B
control/bulk/interrupt
data
programmable
sizes
4 kbytes
ITL buffer
ATL
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