Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
15 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
There are two groups of interrupts represented by group 1 and group 2 in
Figure 13.
A pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus
register). On occurrence of any of these events, the corresponding bit would be set to
logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,
the 6-input OR gate would output a logic 1. This output is ANDed with the value of
MIE (bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause the OPR bit in
the Hc
PInterrupt register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The Hc
PInterrupt and HcPInterruptEnable registers work in the
same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt
group 2. The output from the 6-input OR gate is connected to a latch, which is
controlled by InterruptPinEnable (bit 0 of the HcHardwareConguration register).
In the event in which the software wishes to temporarily disable the interrupt output of
the ISP1160 Host Controller, the following procedure should be followed:
1. Make sure that the InterruptPinEnable bit in the HcHardwareConguration
register is set to logic 1.
2. Clear all bits in the Hc
PInterrupt register.
3. Set the InterruptPinEnable bit to logic 0.
Fig 13. HC interrupt logic.
004aaa102
SOFITLInt
ATLInt
AllEOTInterrupt
OPR_Reg
HCSuspended
HcPInterrupt
register
HcInterruptEnable
register
HcInterruptStatus
register
ClkReady
RHSC
FNO
UE
RD
SF
SO
RHSC
FNO
UE
RD
SF
SO
MIE
OR
SOFITLInt
ATLInt
AllEOTInterrupt
OPR_Reg
HCSuspended
HcPInterruptEnable
register
ClkReady
OR
LATCH
INT
group 2
InterruptPinEnable
HcHardwareConfiguration
register
group
1
LE