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参数资料
| 型号： | 935270523518 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64 |
| 文件页数： | 4/93页 |
| 文件大小： | 2118K |
| 代理商： | 935270523518 |
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Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 03 — 27 February 2003
12 of 89
9397 750 10765
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
8.4 Microprocessor read/write the ISP1160’s internal FIFO buffer RAM
by PIO mode
Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register elds. Therefore, accessing the
ISP1160’s internal FIFO buffer RAM is just like accessing the internal control
registers in multiple data phases.
Figure 9 shows a complete access cycle of the ISP1160’s internal FIFO buffer RAM.
For a write cycle, the microprocessor rst writes the FIFO buffer RAM’s command
code to the command port, and then writes the data words one by one to the data
port until half of the transfer’s byte count is reached. The HcTransferCounter register
(22H - Read, A2H - Write) is used to specify the byte count of a FIFO buffer RAM’s
read cycle or write cycle. Every access cycle must be in the same access direction.
The read cycle procedure is similar to the write cycle.
8.5 Microprocessor read/write the ISP1160’s internal FIFO buffer RAM
by DMA mode
The DMA interface between a microprocessor and the ISP1160 is shown in Figure 4.
When doing a DMA transfer, at the beginning of every burst the ISP1160 outputs a
DMA request to the microprocessor via pin DREQ. After receiving this signal, the
microprocessor will reply with a DMA acknowledge to the ISP1160 via pin DACK, and
at the same time, do the DMA transfer through the data bus. In the DMA mode, the
microprocessor must still issue a RD or WR signal to the ISP1160’s RD or WR pin.
The ISP1160 will repeat the DMA cycles until it receives an EOT signal to terminate
the DMA transfer.
The ISP1160 supports both external and internal EOT signals. The external EOT
signal is received as input from the ISP1160’s EOT pin: it generally comes from the
external microprocessor. The internal EOT signal is generated by the ISP1160
internally.
To select either, set the DMA conguration registers. For example, for the HC, setting
bit 2 of the HcDMAConguration register (21H - Read, A1H - Write) to logic 1 will
enable the DMA counter for DMA transfer. When the DMA counter reaches the value
of HcTransferCounter register, the internal EOT signal will be generated to terminate
the DMA transfer.
The ISP1160 supports either single-cycle DMA operation or burst mode DMA
operation; see Figure 10 and Figure 11.
Fig 9.
The ISP1160’s internal FIFO buffer RAM access cycle.
MGT941
read/write data
#1 (16 bits)
FIFO buffer RAM access cycle (transfer counter = 2N)
t
read/write data
#2 (16 bits)
read/write data
#N (16 bits)
write command
(16 bits)
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