参数资料
型号: A28F200BR-T
厂商: Intel Corp.
英文描述: 2-MBIT (128K x 16) Boot Block Flash Memory(2兆位 (128K x 16) 引导块闪速存储器)
中文描述: 2兆位(128K的× 16)引导块闪存(2兆位(128K的× 16)引导块闪速存储器)
文件页数: 24/36页
文件大小: 440K
代理商: A28F200BR-T
A28F200BR
E
24
ADVANCE INFORMATION
5.0
OPERATING CONDITIONS
Table 9. Temperature and V
CC
Operating Conditions
Parameter
Symbol
Notes
Min
Max
Units
T
A
Operating Temperature
-40
+125
°C
V
CC
V
CC
Supply Voltage (10%)
4.50
5.50
Volts
5.1
Applying V
CC
Voltages
If the V
CC
ramp rate is greater than 0.01 V/μs, a
delay of 2 μs is required before any device
operation can be initiated. This includes array or
status read, command writes and program or erase
operations. The 2 μs are measure beginning from
the time V
CC
reaches V
CCMIN
(4.5V). This delay is
not tied to the operation of the reset input. It is
recommended that the device be held in reset (RP#
= GND) while V
CC
is less than V
CCMIN
.
If the V
CC
ramp rate is less than 0.01 V/μs, no delay
is required once V
CC
has reached V
CCMIN
.
V
CC
Ramp Rate
Required Timing
1V/100
μ
s
No delay required.
> 1V/100
μ
s
A delay time of 2
μ
s is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay
is
measured beginning from the time V
CC
reaches V
CCMIN
(4.5V for 5V operation).
NOTES:
1.
2.
3.
These requirements must be strictly followed to guarantee all other read and write specifications.
Any time the V
CC
supply drops below V
CCMIN
, the chip may be reset, aborting any operations pending or in progress.
These guidelines must be followed for any V
CC
transition from GND.
相关PDF资料
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