参数资料
| 型号： | A3PE600-PQG208I |
| 厂商： | Microsemi SoC |
| 文件页数： | 24/162页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 600000 GATES 208-PQFP |
| 标准包装： | 24 |
| 系列： | ProASIC3E |
| RAM 位总计： | 110592 |
| 输入/输出数： | 147 |
| 门数： | 600000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 208-BFQFP |
| 供应商设备封装： | 208-PQFP（28x28） |
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ProASIC3E Device Family Overview
1-6
Revision 13
Pro I/Os with Advanced I/O Standards
The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-ended,
differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two
per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is
subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8
to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given
VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that
reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)
ProASIC3E banks support M-LVDS with 20 multi-drop points.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Specifying I/O States During Programming
You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for
PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information.
Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have
limited display of Pin Numbers only.
1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during
programming.
2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator
window appears.
3. Click the Specify I/O States During Programming button to display the Specify I/O States During
Programming dialog box.
4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header.
Select the I/Os you wish to modify (Figure 1-3 on page 1-7).
5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings
for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state
settings:
1 – I/O is set to drive out logic High
0 – I/O is set to drive out logic Low
Last Known State – I/O is set to the last value that was driven out prior to entering the
programming mode, and then held at that value during programming
Z -Tri-State: I/O is tristated
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A3PE600-PQG896 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-PQG896ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-PQG896I | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| A3PE600-PQG896PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
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