参数资料
型号: A3PE600-PQG208I
厂商: Microsemi SoC
文件页数: 65/162页
文件大小: 0K
描述: IC FPGA 600000 GATES 208-PQFP
标准包装: 24
系列: ProASIC3E
RAM 位总计: 110592
输入/输出数: 147
门数: 600000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
ProASIC3E Flash Family FPGAs
Revision 13
5-7
v2.0
(continued)
Table 3-6 Temperature and Voltage Derating Factors for Timing Delays was
updated.
3-5
Table 3-5 Package Thermal Resistivities was updated.
3-5
Table 3-10 Different Components Contributing to the Dynamic Power
Consumption in ProASIC3E Devices was updated.
3-8
tWRO and tCCKH were added to Table 3-94 RAM4K9 and Table
3-95 RAM512X18.
3-74 to
3-74
The note in Table 3-24 I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
3-23
Figure 3-43 Write Access After Write onto Same Address, Figure 3-44 Read
Access After Write onto Same Address, and Figure 3-45 Write Access After
Read onto Same Address are new.
3-71 to 3-
73
Figure 3-53 Timing Diagram was updated.
3-80
Notes were added to the package diagrams identifying if they were top or bottom
view.
N/A
The A3PE1500 "208-Pin PQFP" table is new.
4-4
The A3PE1500 "484-Pin FBGA" table is new.
4-18
The A3PE1500 "A3PE1500 Function" table is new.
4-24
Advance v0.6
(January 2007)
In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was
changed for the FG484 and FG676 packages.
ii
Advance v0.5
(April 2006)
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-8 Very-Long-Line Resources was updated.
2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated.
2-28
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
The "RESET" section was updated.
2-25
The "RESET" section was updated.
2-27
B-LVDS and M-LDVS are new I/O standards added to the datasheet.
N/A
The term flow-through was changed to pass-through.
N/A
Figure 2-8 Very-Long-Line Resources was updated.
2-8
The footnotes in Figure 2-27 CCC/PLL Macro were updated.
2-28
The Delay Increments in the Programmable Delay Blocks specification in Figure
2-24 ProASIC3E CCC Options.
2-24
The "SRAM and FIFO" section was updated.
2-21
The "RESET" section was updated.
2-25
The "WCLK and RCLK" section was updated.
2-25
Revision
Changes
Page
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