- 您现在的位置：买卖IC网 > PDF目录294843 > ACS8509 ATM/SONET/SDH SUPPORT CIRCUIT, PQFP100 PDF资料下载
参数资料
| 型号： | ACS8509 |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 10/68页 |
| 文件大小： | 703K |
| 代理商： | ACS8509 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 2.00/January 2006 Semtech Corp.
Page 18
www.semtech.com
ACS8509 SETS
The value in the chip_id location (address 00 & 01) is
checked to see if it matches the ID number of the
ACS8509 (value 213E). Upon a successful number
match, the remaining data from the ROM is used to set
the internal register values. Only 64 locations in the ROM
are required.
Register Set
All registers are 8-bits wide, organized with the most-
significant bit positioned in the left-most bit, with bit
significance decreasing towards the right most bit. Some
registers carry several individual data fields of various
sizes, from single-bit values (e.g. flags) upwards. Several
data fields are spread across multiple registers; their
organization is shown in the register map, Table 13.
Configuration Registers
Each configuration register reverts to a default value on
power-up or following a reset. Most default values are
fixed, but some will be pinsettable. All configuration
registers can be read out over the microprocessor port.
Status Registers
The Status Registers contain readable registers. They may
all be read from outside the chip but are not writeable
from outside the chip (except for a clearing operation). All
status registers are read via shadow registers to avoid
data hits due to dynamic operation. Each individual status
register has a unique location.
Register Access
Most registers are of one of two types, configuration
registers or status registers, the exceptions being the
chip_ID and chip_revision registers. Configuration
registers may be written to or read from at any time (the
complete 8-bit register must be written, even if only one
bit is being modified). All status registers may be read at
any time and, in some status registers (such as the
sts_interrupts register), any individual data field may be
cleared by writing a “1” into each bit of the field (writing a
“0” value into a bit will not affect the value of the bit). A
description of each register is given in the Register Map,
and Register Map Description.
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ (active
High). Bits in the interrupt status register
are set (high) by the following conditions:
1. Any reference source becoming valid or going invalid.
2. A change in the operating state (e.g. Locked, Holdover
etc.)
3. A brief loss of the currently selected reference source.
All interrupt sources are maskable via the mask register,
each one being enabled by writing a “1” to the appropriate
bit. Any unmasked bit set in the interrupt status register
will cause the interrupt request pin to be asserted (high).
All interrupts are cleared by writing a “1” to the bit(s) to be
cleared in the status register. When all pending
unmasked interrupts are cleared the interrupt pin will go
inactive (low).
The loss of the currently selected reference source will
eventually cause the input to be considered invalid,
triggering an interrupt. The time taken to raise this
interrupt is dependant on the leaky bucket configuration
of the activity monitors. The fastest leaky bucket setting
will still take up to 128 ms to trigger the interrupt. The
interrupt caused by the brief loss of the currently selected
reference source is provided to facilitate very fast source
failure detection if desired. It is triggered after missing just
a couple of cycles of the reference source. Some
applications require the facility to switch downstream
devices based on the status of the reference sources. In
order to provide extra flexibility, it is possible to flag the
“main reference failed” interrupt (addr 06, bit 6) on the
pin TDO. This is simply a copy of the status bit in the
interrupt register and is independent of the mask register
settings. The bit is reset by writing to the interrupt status
register in the normal way. This feature can be enabled
and disabled by writing to bit 6 of register 48Hex.
Register Map
Shaded areas in the map are “don’t care” and writing
either 0 or 1 will not affect any function of the device. Bits
labelled Set to 0 or Set to 1 must be set as stated during
initialization of the device, either following power-up, or
after a power-on reset (POR). Failure to correctly set these
bits may result in the device operating in an unexpected
way.
Some registers do not appear in this list. These are either
not used, or have test functionality. Do not write to any
undefined registers as this may cause the device to
operate in a test mode. If an undefined register has been
inadvertently addressed, the device should be reset to
ensure the undefined registers are at default values.
相关PDF资料 |
PDF描述 |
|---|---|
| ACS8946T | ATM/SONET/SDH SUPPORT CIRCUIT, QCC48 |
| ACS8946 | ATM/SONET/SDH SUPPORT CIRCUIT, QCC48 |
| ACT-141223-2R | 1200 MHz - 1400 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
| ACT-141223-4R | 1200 MHz - 1400 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
| ACT-141223-4 | 1200 MHz - 1400 MHz RF/MICROWAVE NARROW BAND LOW POWER AMPLIFIER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACS8509T | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
| ACS8510 | 制造商:Semtech Corporation 功能描述:Timing Source 100-Pin LQFP |
| ACS8510_03 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
| ACS8510REV2.1 | 制造商:Semtech Corporation 功能描述:Timing Source 100-Pin LQFP |
| ACS8510REV2.1SETS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
发布紧急采购，3分钟左右您将得到回复。