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参数资料
| 型号： | ACS8509 |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 3/68页 |
| 文件大小： | 703K |
| 代理商： | ACS8509 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 2.00/January 2006 Semtech Corp.
Page 11
www.semtech.com
ACS8509 SETS
the frequency outside the hold-in range for long enough to
be detected, whilst the signal will also be rejected if the
eye closes sufficiently to affect the signal purity). The
“8klock” mode should be engaged for high jitter tolerance
according to these masks. All reference clock ports are
monitored for quality, including frequency offset and
general activity. Single short-term interruptions in
selected reference clocks may not cause
rearrangements, whilst longer interruptions, or multiple,
short-term interruptions, will cause rearrangements, as
will frequency offsets which are sufficiently large or
sufficiently long to cause loss-of-lock in the phase-locked
loop. The failed reference source will be removed from the
priority table and declared as unserviceable, until its
perceived quality has been restored to an acceptable
level.
The registers sts_curr_inc_offset (address 0C, 0D, 07)
report the frequency of the DPLL with respect to the
external TCXO frequency. This is a 19-bit signed number
with one LSB representing 0.0003 ppm (range of
±80 ppm). Reading this regularly can show how the
currently locked source is varying in value e.g. due to
wander on its input.
The ACS8509 performs automatic frequency monitoring
with an acceptable input frequency offset range of
±16.6 ppm. The ACS8509 DPLL has a programmable
frequency limit of ±80 ppm. If the range is programmed to
be > 16.6 ppm, the frequency monitors should be
disabled so the input reference source is not
automatically rejected as out of frequency range.
Notes: (i) The frequency acceptance and generation range will be ±4.6 ppm around the required frequency when the external crystal
frequency accuracy is within a tolerance of ±4.6 ppm.
(ii) The fundamental acceptance range and generation range is ± 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This is
the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps.
Table 7 Input Reference Source Jitter Tolerance
Jitter Tolerance
Frequency Monitor
Acceptance Range
Frequency Acceptance
Range (Pull-in)
Frequency Acceptance
Range (Hold-in)
Frequency Acceptance
Range (Pull-out)
G.703
±16.6 ppm
±4.6 ppm
(see Note (i))
±4.6 ppm
(see Note (i))
±4.6 ppm
(see Note (i))
G.783
G.823
±9.2 ppm
(see Note (ii))
±9.2 ppm
(see Note (ii))
±9.2 ppm
(see Note (ii))
GR-1244-CORE
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ACS8509T | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
| ACS8510 | 制造商:Semtech Corporation 功能描述:Timing Source 100-Pin LQFP |
| ACS8510_03 | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
| ACS8510REV2.1 | 制造商:Semtech Corporation 功能描述:Timing Source 100-Pin LQFP |
| ACS8510REV2.1SETS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Synchronous Equipment Timing Source for SONET or SDH Network Elements |
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