参数资料
型号: AD5371BSTZ
厂商: Analog Devices Inc
文件页数: 24/29页
文件大小: 0K
描述: IC DAC 14BIT 40CH SER 80-LQFP
标准包装: 1
设置时间: 20µs
位数: 14
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 40
电压电源: 模拟和数字,双 ±
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-LQFP
供应商设备封装: 80-LQFP(12x12)
包装: 托盘
输出数目和类型: 40 电压,单极;40 电压,双极
采样率(每秒): *
AD5371
Rev. B | Page 3 of 28
GENERAL DESCRIPTION
The AD53711 contains 40 14-bit DACs in a single 80-lead LQFP
or 100-ball CSP_BGA. The device provides buffered voltage
outputs with a span of 4× the reference voltage. The gain and
offset of each DAC can be independently trimmed to remove
errors. For even greater flexibility, the device is divided into five
groups of eight DACs. Three offset DACs allow the output range
of the groups to be adjusted. Group 0 can be adjusted by Offset
DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2
to Group 4 can be adjusted by Offset DAC 2.
The AD5371 offers guaranteed operation over a wide supply
range, with VSS from 16.5 V to 4.5 V and VDD from 9 V to
16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
The AD5371 has a high speed serial interface that is compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards
and can handle clock speeds of up to 50 MHz. It also has a
100 MHz low voltage differential signaling (LVDS) serial
interface.
The DAC registers are updated on reception of new data. All the
outputs can be updated simultaneously by taking the LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect
to an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model
Resolution (Bits)
Nominal Output Span
Output Channels
Linearity Error (LSB)
16
4 × VREF (20 V)
16
±4
14
4 × VREF (20 V)
16
±1
16
4 × VREF (20 V)
8
±4
14
4 × VREF (20 V)
8
±1
16
4 × VREF (12 V)
40
±4
AD5371
14
4 × VREF (12 V)
40
±1
16
4 × VREF (12 V)
32
±4
14
4 × VREF (12 V)
32
±1
14
±8.75 V
32
±3
14
±8.75 V
40
±3
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