参数资料
| 型号： | AD5735ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/48页 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD VOLT CUR 64-LFCSP |
| 标准包装： | 1 |
| 设置时间： | 18µs |
| 位数： | 12 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，4 电压 |
| 采样率（每秒）： | * |
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Data Sheet
AD5735
Rev. C | Page 29 of 48
POWER-ON STATE OF THE AD5735
On initial power-up of the AD5735, the state of the power-on
reset circuit is dependent on the power-on condition (POC) pin.
If POC = 0, both the voltage output and current output
channels power up in tristate mode.
If POC = 1, the voltage output channel powers up with
a 30 k pull-down resistor to ground, and the current
output channel powers up in tristate mode.
The output ranges are not enabled, but the default output range
is 0 V to 5 V, and the clear code register is loaded with all 0s.
Therefore, if the user clears the part after power-up, the output
is actively driven to 0 V if the channel has been enabled for clear.
After device power on, or a device reset, it is recommended to
wait 100 μs or more before writing to the device to allow time
for internal calibrations to take place.
SERIAL INTERFACE
The AD5735 is controlled by a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of the serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking (PEC) is enabled, an additional eight
bits must be written to the AD5735, creating a 32-bit serial
interface (see the Packet Error Checking section).
The DAC outputs can be updated in one of two ways: individual
DAC updating or simultaneous updating of all DACs.
Individual DAC Updating
To update an individual DAC, LDAC is held low while data is
clocked into the DAC data register. The addressed DAC output
is updated on the rising edge of SYNC. See Table 3 and Figure 3
for timing information.
Simultaneous Updating of All DACs
To update all DACs simultaneously, LDAC is held high while
data is clocked into the DAC data register. After LDAC is taken
high, only the first write to the DAC data register of each channel
is valid; subsequent writes to the DAC data register are ignored,
although these subsequent writes are returned if a readback is
initiated. All DAC outputs are updated by taking LDAC low
after SYNC is taken high.
VOUT_x
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
AMPLIFIERS
LDAC
SDO
SDIN
12-BIT
DAC
VREFIN
SYNC
DAC DATA
REGISTER
OFFSET
AND GAIN
CALIBRATION
DAC INPUT
REGISTER
SCLK
09961-
072
Figure 72. Simplified Serial Interface of the Input Loading Circuitry
for One DAC Channel
TRANSFER FUNCTION
Table 7 shows the input code to ideal output voltage relationship
for the AD5735 for straight binary data coding of the ±10 V
output range.
Table 7. Input Code to Ideal Output Voltage Relationship
Digital Input
Straight Binary Data Coding
Analog Output
MSB
LSB1
V
OUT
1111
XXXX
+2 V
REF × (2047/2048)
1111
1110
XXXX
+2 V
REF × (2046/2048)
1000
0000
XXXX
0 V
0000
0001
XXXX
2 V
REF × (2047/2048)
0000
XXXX
2 V
REF
1 X = don’t care.
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| AD5735ACPZ-REEL7 | 功能描述:IC DAC QUAD VOLT CUR 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5737 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
| AD5737_12 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
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| AD5737ACPZ-RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
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