参数资料
| 型号： | AD5735ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/48页 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD VOLT CUR 64-LFCSP |
| 标准包装： | 1 |
| 设置时间： | 18µs |
| 位数： | 12 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，4 电压 |
| 采样率（每秒）： | * |
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Data Sheet
AD5735
Rev. C | Page 43 of 48
DC-to-DC Converter External Schottky Diode Selection
The AD5735 requires an external Schottky diode for correct
operation. Ensure that the Schottky diode is rated to handle the
maximum reverse breakdown voltage expected in operation
and that the maximum junction temperature of the diode is not
exceeded. The average current of the diode is approximately
equal to the ILOAD current. Diodes with larger forward voltage
drops result in a decrease in efficiency.
DC-to-DC Converter Compensation Capacitors
Because the dc-to-dc converter operates in discontinuous conduc-
tion mode, the uncompensated transfer function is essentially a
single-pole transfer function. The pole frequency of the transfer
function is determined by the output capacitance, input and output
voltage, and output load of the dc-to-dc converter. The AD5735
uses an external capacitor in conjunction with an internal 150 k
resistor to compensate the regulator loop.
Alternatively, an external compensation resistor can be used in
series with the compensation capacitor by setting the DC-DC
comp bit in the dc-to-dc control register (see Table 28). In this
case, a resistor of ~50 k is recommended. The advantages of this
configuration are described in the AICC Supply Requirements—
Slewing section. For typical applications, a 10 nF dc-to-dc com-
pensation capacitor is recommended.
DC-to-DC Converter Input and Output Capacitor
Selection
The output capacitor affects the ripple voltage of the dc-to-dc
converter and indirectly limits the maximum slew rate at which
the channel output current can rise. The ripple voltage is caused
by a combination of the capacitance and the equivalent series
resistance (ESR) of the capacitor. For typical applications, a
ceramic capacitor of 4.7 F is recommended. Larger capacitors
or parallel capacitors improve the ripple at the expense of
reduced slew rate. Larger capacitors also affect the current
Supply Requirements—Slewing section). The capacitance at
the output of the dc-to-dc converter should be >3 F under all
operating conditions.
The input capacitor provides much of the dynamic current
required for the dc-to-dc converter and should be a low ESR
component. For the AD5735, a low ESR tantalum or ceramic
capacitor of 10 F is recommended for typical applications.
Ceramic capacitors must be chosen carefully because they can
exhibit a large sensitivity to dc bias voltages and temperature.
X5R or X7R dielectrics are preferred because these capacitors
remain stable over wider operating voltage and temperature
ranges. Care must be taken if selecting a tantalum capacitor to
ensure a low ESR value.
AICC SUPPLY REQUIREMENTS—STATIC
The dc-to-dc converter is designed to supply a VBOOST_x voltage of
VBOOST_x = IOUT × RLOAD + Headroom
(2)
See Figure 51 for a plot of headroom supplied vs. output
current. Therefore, for a fixed load and output voltage, the
output current of the dc-to-dc converter can be calculated
by the following formula:
CC
V
BOOST
OUT
CC
AV
η
V
I
AV
Efficiency
Out
Power
AI
BOOST
×
=
×
=
(3)
where:
IOUT is the output current from IOUT_x in amperes.
ηV
BOOST
and Figure 54).
AICC SUPPLY REQUIREMENTS—SLEWING
The AICC current requirement while slewing is greater than in
static operation because the output power increases to charge
the output capacitance of the dc-to-dc converter. This transient
current can be quite large (see Figure 79), although the methods
described in the Reducing AICC Current Requirements section
can reduce the requirements on the AVCC supply.
If not enough AICC current can be provided, the AVCC voltage
drops. Due to this AVCC drop, the AICC current required for
slewing increases further, causing the voltage at AVCC to drop
further (see Equation 3). In this case, the VBOOST_x voltage and,
therefore, the output voltage, may never reach their intended
values. Because the AVCC voltage is common to all channels, this
voltage drop may also affect other channels.
0
5
10
15
20
25
30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
m
A
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
AI
CC
CURRE
NT
(
A)
TIME (ms)
AICC
IOUT
VBOOST
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
09961-
184
Figure 79. AICC Current vs. Time for 24 mA Step Through 1 k Load
with Internal Compensation Resistor
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| AD5735ACPZ-REEL7 | 功能描述:IC DAC QUAD VOLT CUR 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5737 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
| AD5737_12 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
| AD5737ACPZ | 功能描述:IC DAC QUAD 12BIT CUR 64-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5737ACPZ-RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
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