参数资料
| 型号： | AD5757ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/44页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT QUAD 64-LFCSP |
| 特色产品： | AD5755 / AD5755-1 / AD5757 DACs |
| 标准包装： | 1 |
| 设置时间： | 15µs |
| 位数： | 16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 管件 |
| 输出数目和类型： | * |
| 采样率（每秒）： | * |
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Data Sheet
AD5757
Rev. D | Page 23 of 44
THEORY OF OPERATION
The AD5757 is a quad, precision digital-to-current loop
converter designed to meet the requirements of industrial
process control applications. It provides a high precision, fully
integrated, low cost, single-chip solution for generating current
loop outputs. The current ranges available are 0 mA to 20 mA,
0 mA to 24 mA, and 4 mA to 20 mA. The desired output
configuration is user selectable via the DAC control register.
On-chip dynamic power control minimizes package power
dissipation in current mode.
DAC ARCHITECTURE
The DAC core architecture of the AD5757 consists of two
matched DAC sections. A simplified circuit diagram is shown
in Figure 48. The four MSBs of the 16-bit data-word are
decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 12 bits of the data-word
drive Switch S0 to Switch S11 of a 12-bit voltage mode R-2R
ladder network.
12-BIT R-2-R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
2R
S0
S1
S11
E1
E2
E15
VOUT
2R
09225-
069
Figure 48. DAC Ladder Structure
The voltage output from the DAC core is converted to a current
(see Figure 49), which is then mirrored to the supply rail so that
the application simply sees a current source output. The current
outputs are supplied by VBOOST_x.
16-BIT
DAC
VBOOST_x
R2
T2
T1
R3
IOUT_x
RSET
A1
A2
09225-
071
Figure 49. Voltage-to-Current Conversion Circuitry
Reference Buffers
The AD5757 can operate with either an external or internal
reference. The reference input requires a 5 V reference for
specified performance. This input voltage is then buffered
before it is applied to the DAC.
POWER-ON STATE OF THE AD5757
On power-up of the AD5757, the IOUT_x pins are in tristate mode.
After device power-on or a device reset, it is recommended to
wait 100 μs or more before writing to the device to allow time
for internal calibrations to take place.
SERIAL INTERFACE
The AD5757 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking, or PEC (see the Device Features
section), is enabled, an additional eight bits must be written to
the AD5757, creating a 32-bit serial interface.
There are two ways in which the DAC outputs can be updated:
individual updating or simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the DAC data register. The addressed DAC output is updated on
the rising edge of SYNC. See Table 3 and Figure 3 for timing
information.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the DAC data register. Only the first write to each channel’s
DAC data register is valid after LDAC is brought high. Any subse-
quent writes while LDAC is still held high are ignored, although
they are loaded into the DAC data register. All the DAC outputs
are updated by taking LDAC low after SYNC is taken high.
VOUT_x
DAC
REGISTER
INTERFACE
LOGIC
OUTPUT
I/V AMPLIFIER
LDAC
SDO
SDIN
16-BIT
DAC
VREFIN
SYNC
DAC DATA
REGISTER
OFFSET
AND GAIN
CALIBRATION
DAC INPUT
REGISTER
SCLK
09225-
072
Figure 50. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
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相关代理商/技术参数 |
参数描述 |
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| AD5757ACPZ-REEL7 | 功能描述:IC DAC 16BIT QUAD IOUT 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD5757X | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
| AD575JD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD575JN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD575KD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
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