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参数资料
| 型号： | AD6623ABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | CSPBGA-196 |
| 文件页数： | 18/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623ABC |
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REV. 0
AD6623
–18–
–
2
x
–
1
to 2
x
–
1
–
2
–
y
in 2
–
y
steps.
The range limits are tabulated in
Table IV for each
bus. The hexadecimal values are bit-exact and
each MSB has nega
tive weight. Note that the Product bus range is
limited by result of the
multiplication and the two most significant
bits are the same except in one case.
DMEM
32 16
CMEM
256 16
INPUT
ACCUMULATOR
4.18
PRODUCT
1.15
INPUT
1.15
COEF
1.15
2.18
1.17
OUTPUT
2
0
, 2
–
1
, 2
–
2
, OR 2
–
3
Figure 19. Interpolating FIR Filter Block Diagram
The RCF realizes a FIR filter with optional interpolation. The FIR
filter can produce impulse responses up to 256 output samples
long. The FIR response may be interpolated up to a factor of 256,
although the best filter performance is usually achieved when the
RCF interpolation factor (L
RCF
) is confined to eight or below. The
256 16 coefficient memory (CMEM) can be divided among an
arbitrary number of filters, one of which is selected by the Coef-
ficient Offset Pointer (channel address 0x0B). The polyphase
implementation is an efficient equivalent to an integer up-sampler
followed FIR filter running at the interpolated rate.
The AD6623 RCF realizes a sum-of-products filter using a polyphase
implementation. This mode is equivalent to an interpolator followed
by a FIR filter running at the interpolated rate.
In the functional
diagram below, the interpolating block increases the rate by the RCF
interpolation factor (L
RCF
) by inserting L
RCF
–
1 zero valued samples
between every input sample.
The next block
is a filter with a finite
impulse response length (N
RCF
) and an impulse
response of h[n],
where n is an integer from 0 to N
RCF
–
1.
The difference equation for Figure 20 is written below, where h[n]
is the RCF impulse response, b[n] is the interpolated input sample
sequence at point
‘
b
’
in the diagram above, and c[n] is the output
sample sequence at point
‘
c
’
in Figure 20.
N
RCF
TAP
FIR FILTER
h[n]
L
RCF
f
IN
L
RCF
b
a
c
f
IN
f
IN
L
RCF
Figure 20. RCF Interpolation
c n
=
h n
b n
k
N
RCF
∑
×
]
k 0
–
–
1
(5)
This difference equation can be described by the transfer function
from point
‘
b
’
to
‘
c
’
as:
H
z
h n
z
bc
k
N
RCF
( )
–
–
=
∑
=
×
0
1
1
(6)
The actual implementation of this filter uses a polyphase decom-
position
to skip the multiply-accumulates when b[n
–
k] is zero.
Compared to the diagram above, this implementation has the benefits
of reducing by a factor of L
RCF
both the time needed
to calculate
an output and the required data memory (DMEM). The price of
these benefits is that the user must place the coefficients into the coefficient
memory (CMEM) indexed by the interpolation phase. The process of
selecting the coefficients and placing them into the CMEM is broken
into three steps shown below.
The FIR accepts two
’
s complement I and Q samples from the serial
port with a fixed-point resolution of 16 bits each. When the serial port
provides data with less precision, the LSBs are padded with zeroes.
The Data-Mem stores the most recent 16 I and Q pairs for a total
of 32 words. The size of the Data-Mem limits the RCF impulse
response to 16 L
RCF
output samples. When the data words from
the Serial Port have fewer than 16 bits, the LSBs are padded with
zeroes. The Data-Mem can be accessed through the Microport
from 0x20 to 0x5F above the processing channel
’
s base internal
address, while the channel
’
s Prog bit is set (external address 4).
In order to avoid start-up transients, the Data-Mem should be
cleared before operation. The Prog bit must then be reset to
enable normal operation.
The Coef-Mem stores up to 256 16-bit filter coefficients. The Coef-
Mem can be accessed through the Microport from 0x800 to 0x8FF
above the processing channel
’
s base internal address, while the channel
’
s
Prog bit is set (external address 4). For AD6622 compatibility, the lower
128 words are also mirrored from 0x080 to 0x0FF above the processing
channel
’
s base internal address, while
the Prog
bit is set. To avoid
start-up transients, the Data-Mem should be cleared
before operation.
The Prog bit must
then be reset to enable channel operation.
There is a single Multiply-Accumulator (MAC) on which both the
I and Q operations must be interleaved. Two CLK cycles are required
for the MAC to multiply each coefficient by an I and Q pair. The
MAC is also used for four additional CLK cycles if the All-pass
Phase Equalizer is active.
The size of the Data-Mem and Coef-Mem combined with the
speed of the MAC determine the total number of the taps per
phase (T
RCF
) that may be calculated. T
RCF
is the number of
RCF input samples that influence each RCF output sample.
The maximum available T
RCF
is calculated by the equation below.
T
least of
floor
L
floor
f
f
APE
RCF
RCF
CLK
×
SDO
≤
×
16
256
2
2
,
,
–
(7)
The impulse response length at the output of the RCF is deter
mined
by the product of the number of interfering input samples
(T
RCF
)
and the RCF interpolation factor (L
RCF
), as shown by
equation
(8) below. The values of N
RCF
and T
RCF
are programmed
into control
registers. L
RCF
is not a control register, but N
RCF
and T
RCF
must
be set so that L
RCF
is an integer. If the integer interpolation by
the RCF results in an inconvenient sample rate at the output of
the RCF, the desired output rate can usually be
achieved by
selecting non-integer interpolation in the resampling
CIC
2
filter.
N
T
L
RCF
RCF
RCF
=
×
(8)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6623ABCZ | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA |
| AD6623AS | 制造商:Analog Devices 功能描述:Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
| AD6623ASZ | 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6623BC/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
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