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参数资料
| 型号： | AD6623ABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | CSPBGA-196 |
| 文件页数： | 26/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623ABC |
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REV. 0
AD6623
–26–
drive two DACs. Channels are added in pairs (A + B), (C + D)
as shown in Figure 32.
CHANNELS
A + B
AD6623
OUT
[17:0]
IN/OUT
[17:0]
CHANNELS
C + D
14-BIT
DAC
14-BIT
DAC
Figure 32. AD6623 Driving Two DACs
The Wideband Output Bus may be interpreted as a two
’
s comple-
ment number or as an offset binary number as defined by bit 1 of the
Summation Mode Control Register at address 0x000. When this
bit is high, then the Wideband Output is in two
’
s complement mode
and when it is low it is configured for offset binary output data.
The MSB (bit 17) of the Wideband Output Bus is typically used
as a guard bit for the purpose of clipping the wideband output
bus when bit 0 of the Summation Mode Control Register at
address 0x000 is high. If clip detection is enabled then bit 17 of
the output bus is not used as a data bit. Instead, bit 16 will become
the MSB and is connected to the MSB of the DAC. Configuring
the DAC in this manner gives the summation block a gain of 0 dB.
When clip detection is not enabled and bit 17 is used as a data
bit then the summation block will have a gain of
–
6.02 dB.
There are two data output modes. The first is offset binary.
This mode is used only when driving offset binary DACs. Two
’
s
complement mode may be used in one of two circumstances. The
first is when driving a DAC that accepts two
’
s complement data.
The second is when driving another AD6623 in cascade mode.
When clipping is enabled, the two
’
s complement mode output bus
will clip to 0x2FFFF for output signals more positive than the
output can express and it will clip to 0x3000 for signals more nega-
tive than the output can express. In offset binary mode the output
bus will clip to 0x3FFFF for output signals more positive than
the output can express and it will clip to 0x2000 for signals more
negative than the output can express.
The Wideband Input is always interpreted as an 18-bit two
’
s
complement number and is typically connected to the Wideband
Output Bus of another AD6623 in order to send more than four
carriers to a single DAC. The Output Bus of the preceeding
AD6623 should be configured in two
’
s complement mode and
clip detection disabled. The 18-bit resolution insures that the noise
and spur performance of the wideband data stream does not become
the limiting factor as large numbers of carriers are summed.
There is a two-clock cycle latency from the Wideband Input Bus
to the Wideband Output Bus. This latency may be calibrated out
of the system by use of the Start Hold-Off counter. The preceding
AD6623 in a cascaded chain can be started two CLK
cycles before
the following AD6623 is started and the data from each AD6623
will arrive at the DAC on the same clock cycle. In systems where the
individual signals are not correlated, this is usually not necessary.
The AD6623 is capable of outputting both real and complex data.
When in Real mode the QIN input is tied low signaling that all
inputs on the Wideband Input Bus are real and that all outputs
on the Wideband Output Bus are real. The Wideband Input Bus
will be pulled low and no data will be added to the composite
signal if this port is unused (not connected).
If complex data is desired there are two ways this can be obtained.
The first method is to simply set the QIN input of the
AD6623
high and to set the Wideband Input Bus low. This allows
the AD6623
to output complex data on the Wideband Output Bus. The I data
samples would be identified when QOUT is low
and
the Q data
samples would be identified when QOUT is high. The
second
method of obtaining complex data is to provide a QIN signal that
toggles on every rising edge of the CLK. This could be obtained
by connecting the QOUT of another AD6623 to QIN as shown
in Figure 33. In a cascaded system the QIN of the first AD6623
in the chain would typically be tied high and the QOUT of the
first AD6623 would be connected to the QIN of the following
part. All AD6623s will synchronize themselves to the QIN input
so that the proper samples are always paired and the Wideband
Output bus represents valid complex data samples. Table XV
shows different parallel input and output data bus formats as a
function of QIN and QOUT.
Table XV. Valid Output Bus Data Modes
Wideband Input
IN[17:0]
Output Data Type
OUT[17:0], QOUT
QIN
Low
High
Pulsed
Real
Zero
Complex
Real
Complex
Complex
14-BIT
DAC
OUT
[16:3]
IN
[17:0]
OUT
[17:0]
Q
IN
Q
OUT
IN
[17:0]
Q
IN
AD6623
AD6623
LOGIC1
LOGIC0
Figure 33. Cascade Operation of Two AD6623s
SYNCHRONIZATION
Three types of synchronization can be achieved with the AD6623.
These are Start, Hop, and Beam. Each is described in detail below.
The synchronization is accomplished with the use of a shadow
register and a Hold-Off counter. See Figure 34 for a simplistic
schematic of the NCO shadow register and NCO Frequency
Hold-Off counter to understand basic operation. Enabling the
clock (AD6623 CLK) for the Hold-Off counter can occur with
either a Soft_Sync (via the micro port), or a Pin Sync (via the
AD6623 Sync pin, Pin 62). The functions that include shadow
registers to allow synchronization include:
1. Start
2. Hop (NCO Frequency)
3. Beam (NCO Phase Offset)
Start
Refers to the start-up of an individual channel, chip, or multiple
chips. If a channel is not used, it should be put in the Sleep
Mode to reduce power dissipation. Following a hard reset (low
pulse on the AD6623
RESET
pin), all channels are placed in
the Sleep Mode.
Start With No Sync
If no synchronization is needed to start multiple channels or mul-
tiple AD6623s, the following method should be used to initialize
the device.
1. To program a channel, it must first be set to the Program Mode
(bit high) and Sleep Mode (bit high) (Ext Address 4). The
Program Mode allows programming of data memory and coeffi-
cient memory (all other registers are programmable whether in
Program Mode or not). Since no synchronization is used, all
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相关代理商/技术参数 |
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|---|---|
| AD6623ABCZ | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA |
| AD6623AS | 制造商:Analog Devices 功能描述:Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
| AD6623ASZ | 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6623BC/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
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