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参数资料
| 型号： | AD6623AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | PLASTIC, MQFP-128 |
| 文件页数： | 33/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623AS |
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REV. 0
AD6623
–33–
Channel Function Registers (continued)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
2. Update RCF Mode Select registers
marked with
“
2
”
.
3. Ramp Up (if Ramp is enabled)
No Change
No Change
Ch. A RCF FIR
–
PSK Magnitude 0
Ch. A RCF FIR
–
PSK Magnitude 1
Ch. A RCF FIR
–
PSK Magnitude 2
Ch. A RCF FIR
–
PSK Magnitude 3
Ch. A Serial Data Frame Input Select
0x: Internal Frame Request
10: External SDFI Pad
11: Previous Channel
’
s Frame End
Ch. A Serial Data Frame Output Select
0: Serial Data Frame Request
1: Serial Data Frame End
Ch. A Serial Clock Slave (SCS)
SCS = 0: Master Mode
(SCLK is an output)
SCS = 1: Slave Mode
(SCLK is an input)
Ch. A Serial Fine Scale Enable
1
Ch. A Serial Time Slot Sync Enable
(ignored in FIR mode)
Ch. A Ramp Interpolation Enable
Ch. A Ramp Enable
Ch. A Mode 0 Ramp Length, R0
–
1
Ch. A Mode 1 Ramp Length, R1
–
1
Ch. A Ramp Rest Time, Q
(No inputs requested during rest time.)
No Change
No Change
No Change
Ch. A Ramp RAM
No Change
This address is mirrored at 0x900
–
0x97F
and contiguously extended at 0x980
–
0x9FF
0x110
0x111
0x112
0x113
0x114
0x115
0x116
15
–
0
15
–
0
15
–
0
15
–
0
15
–
0
15
–
0
7
–
6
Ch. A RCF Phase EQ Coef1
Ch. A RCF Phase EQ Coef2
Unused
Unused
Unused
Unused
Unused
5
Unused
4
Unused
3
2
Unused
Unused
1
0
5
–
0
4
–
0
4
–
0
Unused
Unused
Unused
Unused
Unused
0x117
0x118
0x119
0x11A
–
11F
0x120
–
13F
0x140
–
17F
Unused
Ch. A Data RAM
Unused
Unused
Ch. A Coefficient RAM
15
–
0
15
–
14
13
–
0
15
–
0
0x180
–
1FF
NOTES
1
Clear on
RESET
.
2
These bits update after a Start or a Beam Sync. See CR 0x10F.
3
Allows dynamic updates.
(0x000) Summation Mode Control
Controls features in the summation block of the AD6623.
Bit 5
–
6:
Reserved.
Bit 4:
Low: Wideband Input Enabled.
High: Wideband Input Disabled.
Bit 3:
Low: Dual Output Disabled.
High: Dual Output Enabled.
Bit 2:
Reserved.
Bit 1:
Low: Output data will be in two
’
s complement.
High: Output data will be in offset binary.
Bit 0:
Low: Over-range will wrap.
High: Over-range will clip to full scale.
(0x001) Sync Mode Control
Bit 7:
Ignores all but the first pin sync.
Bit 6:
Beam on pin Sync.
Bit 5:
Hop on pin Sync.
Bit 4:
High enables the count down of the Start Hold-Off
Counter. The counter is clocked with the AD6623
CLK signal. When it reaches a count of one the Sleep
bit of the appropriate channel(s) is set low to activate
the channel(s).
High enables synchronization of these channels.
See the
Synchronization section of the data sheet for
detailed explanation.
(0x002) BIST Counter
Sets the length, in CLK cycles, of the built-in self test.
(0x003) BIST Result
A read-only register containing the result after a self test. Must be
compared to a known good result for a given setup to determine
pass/fail.
Bit 3
–
0:
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相关代理商/技术参数 |
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|---|---|
| AD6623ASZ | 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6623BC/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
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