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参数资料
| 型号： | AD6623AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | PLASTIC, MQFP-128 |
| 文件页数： | 34/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623AS |
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REV. 0
AD6623
–34–
Channel Function Registers
The following registers are channel-specific.
‘
0xn
’
denotes that
these values are represented as hexadecimal numbers;
‘
n
’
repre-
sents the specified channel. Valid channels are n = 1, 2, 3, and 4.
(0xn00) Start Update Hold-Off Counter
See the Synchronization section for detailed explanation. If no
synchronization is required, this register should be set to 0.
Bit 17
–
16: The Start Sync Select bits are used to set which
sync pin will initiate a start sequence.
Bit 15
–
0:
The Start Update Hold-Off Counter is used to synchro-
nize start
–
up of AD6623 channels and can be used to
synchronize
multiple chips. The Start Update Hold-Off
Counter is clocked by
the AD6623 CLK (master clock).
(0xn01) NCO Control
Bit 1:0
Set the NCO scaling per Table XXI.
Table XXI. NCO Control (0xn01)
Bit 1
Bit 0
NCO Output Level
0
0
1
1
0
1
0
1
–
6 dB (no attenuation)
–
12 dB attenuation
–
18 dB attenuation
–
24 dB attenuation
Bit 2:
High clears the NCO phase accumulator to 0 on
either a Soft Sync or Pin Sync (see Synchronization
for details).
High enables NCO phase dither.
High enables NCO amplitude dither.
Reserved and should be written low.
(0xn02) NCO Frequency
This register is a 32-bit unsigned integer that sets the NCO
Frequency. The NCO Frequency contains a shadow register for
synchronization purposes. The shadow can be read back directly,
the NCO Frequency cannot.
f
FREQUENCY
=
Bit 3:
Bit 4:
Bit 7
–
5:
NCO
CLK
CHANNEL
×
2
32
(26)
(0xn03) NCO Frequency Update Hold-Off Counter
See the Synchronization section for detailed explanation. If no
synchronization is required, this register should be set to 0.
Bit 17
–
16: The Hop Sync Select bits are used to set which sync
pin will initiate a hop sequence.
Bit 15
–
0:
The Hold-Off Counter is used to synchronize the
change of NCO frequencies.
(0xn04) NCO Phase Offset
This register is a 16-bit unsigned integer that is added to the phase
accumulator of the NCO. This allows phase synchronization of
multiple channels of the AD6623(s). The NCO Phase Offset contains
a shadow register for synchronization purposes. The
shadow can
be read back directly, the NCO Phase Offset cannot.
See the
Synchronization section for details.
(0xn05) NCO Phase Offset Update Hold-Off Counter
See the Synchronization section for a detailed explanation. If no
synchronization is required, this register should be set to 0.
Bit 17
–
16: The Phase Sync Select bits are used to set which sync
pin will initiate a phase sync sequence.
Bit 15
–
0:
The Hold-Off Counter is used to synchronize the
change of NCO phases.
(0xn06) CIC Scale
Bits 4
–
0: Sets the CIC scaling per the equation below.
(
See the CIC section for details.
(0xn07) CIC2 Decimation – 1 (M
CIC2
– 1)
This register is used to set the decimation in the CIC2 filter. The
value written to this register is the decimation minus one. The
CIC2 decimation can range from 1 to 512 depending upon the
interpolation of the CIC2. There is no timing error associated
with this decimation. See the CIC2 section for further details.
(0xn08) CIC2 Interpolation – 1 (L
CIC2
– 1)
This register is used to set the interpolation in the CIC2 filter.
The value written to this register is the interpolation minus one.
The CIC2 interpolation can range from 1 to 4096.
L
rCIC2
must
be chosen equal to or larger than M
rCIC2
and both must be cho-
sen such that
a suitable CIC2 Scalar can be chosen. For more
details the CIC2
section should be consulted.
(0xn09) CIC5 Interpolation – 1
This register sets the interpolation rate for the CIC5 filter stage
(unsigned integer). The programmed value is the CIC5 Interpo-
lation
–
1. Maximum interpolation is limited by the CIC scaling
available (See the CIC section).
(0xn0A) Number of RCF Coefficients – 1
This register sets the number of RCF Coefficients and is limited
to a maximum of 256. The programmed value is the number of
RCF Coefficients
–
1. There is an A register and a B register at
this memory location. Value A is used when the RCF is operating
in mode 0 and value B is used when in mode 1. The RCF mode
bit of interest here is bit 6 of address 0xn0C.
(0xn0B) RCF Coefficient Offset
This register sets the offset for RCF Coefficients and is normally
set to 0. It can be viewed as a pointer which selects the portion
of the CMEM used when computing the RCF filter. This allows
multiple filters to be stored in the Coefficient memory space, selecting
the appropriate filter by setting the offset.
(0xn0C) Channel Mode Control 1
Bit 9:
High, selecting compact FIR mode results in 24-bit
serial word length (12 I followed by 12 Q). When
low, selecting compact FIR mode results in 16-bit
serial word length (8 I followed by 8 Q).
Bit 8:
High enables RCF Pseudo-Random Input Select.
Bit 7:
High selects a Pseudo-Random sequence length of
8,388,607. Low selects a Pseudo-Random Sequence
length of 15.
Bits 6
–
4:
Sets the channel input format as shown in Table XXII.
CIC
Scale
ceil
L
L
CIC
CIC
_
=
×
×
(
)
)
log
2
5
4
2
(27)
Table XXII. Channel Inputs
Bit 6
Bit 5
Bit 4
Input Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FIR
/4-DQPSK
GSM
MSK
Compact FIR
8PSK
3 /8-8PSK
QPSK
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相关代理商/技术参数 |
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| AD6623ASZ | 功能描述:IC TSP 4CHAN 104MSPS 128MQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 特色产品:NXP - I2C Interface 标准包装:1 系列:- 应用:2 通道 I²C 多路复用器 接口:I²C，SM 总线 电源电压:2.3 V ~ 5.5 V 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:剪切带 (CT) 安装类型:表面贴装 产品目录页面:825 (CN2011-ZH PDF) 其它名称:568-1854-1 |
| AD6623BC/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
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| AD6624 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
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