参数资料
型号: AD6623AS
厂商: ANALOG DEVICES INC
元件分类: 通信及网络
英文描述: 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP128
封装: PLASTIC, MQFP-128
文件页数: 6/40页
文件大小: 381K
代理商: AD6623AS
REV. 0
–6–
AD6623
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1, 2
Test
Level
AD6623AS
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM Write Timing
:
t
SC
t
HC
t
HWR
t
SAM
t
HAM
t
DRDY
t
ACC
MODE INM Read Timing
:
t
SC
t
HC
t
SAM
t
HAM
t
ZOZ
t
DD
t
DRDY
t
ACC
MICROPROCESSOR PORT, MOTOROLA (MODE = 1)
Control
3
to
CLK Setup Time
Control
3
to
CLK Hold Time
WR(
RW
)
to RDY(
DTACK
) Hold Time
Address/Data to
WR
(RW) Setup Time
Address/Data to RDY(
DTACK
) Hold Time
WR
(RW) to RDY(
DTACK
) Delay
WR
(RW) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
4.5
2.0
8.0
3.0
2.0
4.0
4
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
5
×
t
CLK
9
×
t
CLK
Control
3
to
CLK Setup Time
Control
3
to
CLK Hold Time
Address to
RD
(
DS
) Setup Time
Address to Data Hold Time
Data Three-State Delay
RDY(
DTACK
) to Data Delay
RD
(
DS
) to RDY(
DTACK
) Delay
RD
(
DS
) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
4.5
2.0
3.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
4.0
8
×
t
CLK
10
×
t
CLK
13
×
t
CLK
MODE MNM Write Timing
:
t
SC
t
HC
t
HDS
t
HRW
t
SAM
t
HAM
t
DDTACK
t
ACC
MODE MNM Read Timing:
t
SC
t
HC
t
HDS
t
SAM
t
HAM
t
ZD
t
DD
t
DDTACK
t
ACC
NOTES
1
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs (unless otherwise specified).
3
Specification pertains to control signals: RW, (
WR
),
DS
, (
RD
),
CS
.
Specifications subject to change without notice.
Control
3
to
CLK Setup Time
Control
3
to
CLK Hold Time
DS
(
RD
) to
DTACK
(RDY) Hold Time
RW(
WR
) to
DTACK
(RDY) Hold Time
Address/Data to RW(
WR
) Setup Time
Address/Data to RW(
WR
) Hold Time
DS
(
RD
) to
DTACK
(RDY) Delay
RW(
WR
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
4.5
2.0
8.0
8.0
3.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
Full
IV
4
×
t
CLK
5
×
t
CLK
9
×
t
CLK
Control
3
to
CLK Setup Time
Control
3
to
CLK Hold Time
DS
(
RD
) to
DTACK
(RDY) Hold Time
Address to
DS
(
RD
) Setup Time
Address to Data Hold Time
Data Three-State Delay
DTACK
(RDY) to Data Delay
DS
(
RD
) to
DTACK
(RDY) Delay
DS
(
RD
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
4.0
2.0
8.0
3.0
2.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
×
t
CLK
10
×
t
CLK
13
×
t
CLK
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