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参数资料
| 型号： | AD6624AABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | PLASTIC, BGA-196 |
| 文件页数： | 15/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624AABC |
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REV. 0
AD6624A
–15–
A typical application for this feature would be to take the data
from an AD6600 Diversity ADC to one of the inputs of the
AD6624A. The A/B_OUT from that chip would be tied to the
IEN. One channel within the AD6624A would be then set so
that IEN transition to low is enabled. Another channel would be
configured so that IEN transition to high is enabled. One of the
serial outputs would be configured as the Serial Bus Master and
the other as a serial bus slave and the output bus configured as
shown in Figure 25. This would allow two of the AD6624A
channels to be configured to emulate that AD6620 in diversity
mode. Of course the NCO frequencies and other channel char-
acteristics would need to be set similarly, but this feature allows
the AD6624A to handle interleaved data streams such as found
on the AD6600.
The difference between the IEN transition to high and the IEN
high is found when a system clock is provided that is higher than
the data rate of the converter. It is often advantageous to supply
a clock that runs faster than the data rate so that additional filter
taps can be computed. This naturally provides better filtering.
In order to ensure that other parts of the circuit properly recog-
nize the faster clock in the simplest manner, the IEN transition
to low or high should be used. In this mode, only the first clock
edge that meets the setup and hold times will be used to latch
and process the input data. All other clock pulses are ignored by
front end processing. However, each clock cycle will still pro-
duce a new filter computation pair.
Gain Switching
The AD6624A includes circuitry that is useful in applications
where either large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresh-
olds to be set such that an upper and a lower threshold can
be programmed.
One such use of this may be to detect when an ADC converter
is about to reach full-scale with a particular input condition.
The result would be to provide a flag that could be used to
quickly insert an attenuator that would prevent ADC overdrive.
If 18 dB (or any arbitrary value) of attenuation (or gain) is
switched in, the signal dynamic range of the system will have
been increased by 18 dB. The process begins when the input
signal reaches the upper programmed threshold. In a typical
application, this may be set 1 dB (user-definable) below full-
scale. When this input condition is met, the appropriate LI
(LIA-A, LIA-B, LIB-A, or LIB-B) signal associated with either
the A or B input port is made active. This can be used to switch
the gain or attenuation of the external circuit. The LI signal stays
active until the input condition falls below the lower programmed
threshold. To provide hysteresis, a dwell-time register (see
Memory Map for Input Control Registers) is available to hold
off switching of the control line for a predetermined number of
clocks. Once the input condition is below the lower thresh-
old, the programmable counter begins counting high-speed
clocks. As long as the input signal stays below the lower thresh-
old for the number of high-speed clock cycles programmed, the
attenuator will be removed on the terminal count. However, if
the input condition goes above the lower threshold with the
counter running, it will be reset and must fall below the lower
threshold again to initiate the process. This will prevent unnec-
essary switching between states.
This is illustrated in Figure 23. When the input signal goes
above the upper threshold, the appropriate LI signal becomes
active. Once the signal falls below the lower threshold, the
counter begins counting. If the input condition goes above the
lower threshold, the counter is reset and starts again as shown
in Figure 23. Once the counter has terminated to zero, the LI
signal goes inactive.
“
HIGH
”
DWELL TIME
“
LOW
”
TIME
UPPER THRESHOLD
LOWER THRESHOLD
COUNTER RESTARTS
Figure 23. Threshold Settings for LI
The LI signal can be used for a variety of functions. It can be
used to set the controls of an attenuator DVGA or integrated and
used with an analog VGA. To simplify the use of this feature,
the AD6624A includes two separate gain settings, one when this
line is inactive (rCIC2_QUIET[4:0]) and the other when active
(rCIC2_LOUD[4:0]). This allows the digital gain to be adjusted
to the external changes. In conjunction with the gain setting, a
variable hold-off is included to compensate for the pipeline delay of
the ADC and the switching time of the gain control element.
Together, these two features provide seamless gain switching.
Another use of these pins is to facilitate a gain range hold-off within
a gain-ranging ADC. For converters that use gain ranging to
increase total signal dynamic range, it may be desirable to pro-
hibit internal gain ranging from occurring in some instances.
For such converters, the LI (A or B) signals can be used to hold
this off. For this application, the upper threshold would be set
based on similar criteria. However, the lower threshold would
be set to a level consistent with the gain ranges of the specific
converter. The hold-off delay can then be set appropriately for
any number of factors such as fading profile, signal peak to
average ratio, or any other time-based characteristics that might
cause unnecessary gain changes.
Since the AD6624A has a total of four gain control circuits that
can be used if both A and B Input Ports have interleaved data,
each respective LI pin is independent and can be set to different
set points. It should be noted that the gain control circuits are
wideband and are implemented prior to any filtering elements to
minimize loop delay. Any of the four channels can be set to
monitor any of the possible four input channels (two in normal
mode and four when the inputs are time-multiplexed).
The chip also provides appropriate scaling of the internal data
based on the attenuation associated with the LI signal. In this
manner, data to the DSP maintains a correct scale value through-
out the process, making it totally independent. Since finite
delays are often associated with external gain switching compo-
nents, the AD6624A includes a variable pipeline delay that can
be used to compensate for external pipeline delays or gross
settling times associated with gain/attenuator devices. This delay
may be set up to seven high-speed clocks. These features ensure
smooth switching between gain settings.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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