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参数资料
| 型号： | AD6624AABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | PLASTIC, BGA-196 |
| 文件页数： | 24/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624AABC |
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REV. 0
AD6624A
–24–
1. Note that the time from when RDY (Pin 57) goes high to
when the NCO begins processing data is the contents of the NCO
Freq Hold-Off counter (0x84) plus seven master clock cycles.
2. Write the NCO Freq Hold-Off (0x84) counter to the appro-
priate value (greater than 1 and less then 2
16
–
1
).
3. Write the NCO Frequency register(s) to the new desired
frequency.
4. Write the Hop bit and the Sync(s) bit high (Ext Address 4).
5. This starts the NCO Freq Hold-Off counter counting down.
The counter is clocked with the AD6624A CLK signal. When
it reaches a count of one, the new frequency is loaded into
the NCO.
Hop with Pin Sync
The AD6624A includes four Sync pins to provide the most
accurate synchronization, especially between multiple AD6624s.
Synchronization of hopping to a new NCO frequency with an
external signal is accomplished using the following method:
1. Note that the time from when the Sync pin goes high to when
the NCO begins processing data is the contents of the NCO Freq
Hold-Off counter (0x84) plus five master clock cycles.
2. Write the NCO Freq Hold-Off counter(s) (0x84) to the
appropriate value (greater than 1 and less than 2
16
–
1
).
3. Write the NCO Frequency register(s) to the new desired
frequency.
4. Set the Hop on Pin Sync bit and the appropriate Sync Pin
Enable high.
5. When the selected Sync pin is sampled high by the AD6624A
CLK, it enables the count-down of the NCO Freq Hold-Off
counter. The counter is clocked with the AD6624A CLK
signal. When it reaches a count of one, the new frequency is
loaded into the NCO.
SERIAL OUTPUT DATA PORT
The AD6624A has four configurable serial output ports (SDO0,
SDO1, SDO2, and SDO3). Each port can be operated indepen-
dently of the other, making it possible to connect each to a
different DSP. In the case where a single DSP is required, the
ports can easily be configured to work with a single serial port
on a single DSP. As such, each output may be configured as
either serial master or slave. Additionally, each channel can be
configured independently of the others.
Serial Output Data Format
The AD6624A works with a variety of output data formats.
These include word lengths of 12-, 16-, and 24-bit precision. In
addition to the normal linear binary data format, the AD6624A
offers a floating-point data format to simplify numeric processing.
These formats are 8-bit mantissa with 4-bit exponent, and 12-bit
mantissa and 4-bit exponent. These modes are available regardless
of the bit precision of the serial data frame. In the normal linear
binary data format, a programmable internal 4-bit scaling factor
is used to scale the output. See the RCF Output Scale Factor
section and Control Register above for more details. In all
modes, the data is shifted out of the device in Big Endian format
(MSB first).
In floating-point mode, the chip normally determines the expo-
nent automatically; however, the chip can be forced to use the
same exponent for both the real and imaginary portion of the
data. The choice of exponents favors prevention of numerical
overflow at the expense of small number accuracy. However,
this should not be a problem as small numbers imply numbers
close to zero.
Finally, the AD6624A channel can be forced to use a preselected
scale factor if desired. This allows for a consistent range of data
useful to many applications.
Compact Serial Data Format
Channel data from the AD6624A can be output in a compact
8+4 floating-point format in conjunction with the Common
Exponent model. The 8+4 floating-point format causes the
AD6624A to provide I/Q output data in the form [I mantissa,
8 bits] [I exponent, 4 bits] followed by [Q mantissa, 8 bits] [Q
exponent, 4 bits]. Although the four Q exponent bits normally
would follow the Q mantissa, it is not strictly necessary for these
bits to be provided since its value will be identical to the I exponent
value due to the Common Exponent mode. Since the next I/Q
sample appears internally at the shifter after precisely 20
high-speed clock cycles, the four Q exponent bits are not shifted
out. (The output shifter gives priority to the new sample rather
than the four remaining exponent bits.) The result is that 20
bits are provided as necessary, and these bits contain all the
information necessary to reconstruct the I/Q sample. Note that all
output shifters will be continuously active with this configuration.
The compact serial data mode is enabled by using a total decima-
tion factor of 20 in each channel. The equation below illustrates
how decimation and interpolation factors can be distributed
across the filter blocks:
The RCF control register must also be set to 8+4 floating-point
mode (0xA4 bits 5-4: 01), and the common exponent mode
(0xA4 bit 7: 1). For more information on how the Compact Serial
Data Format can be used to process UMTS signals, please
reference the technical note: Processing Two UMTS Carriers
with 2x Oversampling Using the AD6624A.
Serial Data Frame (Serial Bus Master)
The serial data frame is initiated with the Serial Data Frame Sync
(SDFS0, SDFS1, SDFS2, or SDFS3). As each channel within
the AD6624A completes a filter cycle, data is transferred into the
serial data buffer. In the Serial Bus Master (SBM) mode, the inter-
nal serial controller initiates the SDFS on the next rising edge of
the serial clock. In the AD6624A, there are three different modes
in which the frame sync may be generated as a Serial Bus Master.
In the first mode, the SDFS is valid for one complete clock cycle
prior to the data shift. On the next clock cycle, the AD6624A
begins shifting out the digitally processed data stream. Depend-
ing on the bit precision of the serial configuration, either 12, 16,
or 24 bits of I data are shifted out, followed by 12, 16, or 24
bits of Q data. The format of this data will be in one of the
formats listed above. In the second mode, the SDFS is high for
the entire time that valid bits are being shifted. The SDFS bit
goes high concurrent with the first bit shifted out of the AD6624A.
M
L
M
M
rCIC
rCIC
rCIC
RCF
2
2
5
20
×
×
=
(15)
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相关代理商/技术参数 |
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|---|---|
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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