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参数资料
| 型号： | AD6624AABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | PLASTIC, BGA-196 |
| 文件页数： | 37/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624AABC |
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REV. 0
AD6624A
–37–
JTAG BOUNDARY SCAN
The AD6624A supports a subset of IEEE Standard 1149.1 specifi-
cations. For additional details of the standard, please see
“
IEEE
Standard Test Access Port and Boundary-Scan Architecture,
”
IEEE-1149 publication from IEEE.
The AD6624A has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port and
are listed in the table below. All input JTAG pins are pull-up,
except for TCLK which has a pull-down.
Table XIV. Boundary Scan Test Pins
Name
Pin Number
Description
TRST
TCLK
TMS
TDI
TDO
67
68
69
72
70
Test Access Port Reset
Test Clock
Test Access Port Mode Select
Test Data Input
Test Data Output
The AD6624A supports the op codes as shown below. These
instructions set the mode of the JTAG interface.Address 02 is
the dwell time for input channel A. This sets the
Table XV. Boundary Scan Op Codes
Instruction
Op Code
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
HIGHZ
CLAMP
001
111
010
000
011
100
The Vendor Identification Code can be accessed through the
IDCODE instruction and has the following format.
Table XVI. Vendor ID Code
MSB
Version
Part
Number
Manufacturing
ID #
LSB
Mandatory
0000
0010
0111
1000
1100
000 1110 0101
1
A BSDL file for this device is available; please contact Analog
Devices, Inc. for more information.
EXTEST (3
’
b000) Places the IC into an external boundary-test
mode and selects the boundary-scan register to be connected
between TDI and TDO. During this, the boundary-scan regis-
ter is accessed to drive test data off-chip via boundary outputs
and receive test data off-chip from boundary inputs.
IDCODE (3
’
b001) Allows the IC to remain in its functional
mode and selects device ID register to be connected between
TDI and TDO. Accessing the ID register does not interfere
with the operation of the IC.
SAMPLE/PRELOAD (3
’
b010) Allows the IC to remain in
normal functional mode and selects the boundary-scan register
to be connected between TDI and TDO. The boundary-scan
register can be accessed by a scan operation to take a sample of
the functional data entering and leaving the IC. Also, test
data can be preloaded into the boundary scan register before
an EXTEST instruction.
HIGHZ (3
’
b011) Sets all outputs to high impedance state.
Selects the 1-bit bypass register to be connected between
TDI and TDO.
CLAMP (3
’
b100) Sets the outputs of the IC to logic levels
determined by the boundary-scan register and selects the 1-bit
bypass register to be connected between TDI and TDO. Before
this instruction, boundary-scan data can be preloaded with
the SAMPLE/PRELOAD instruction.
BYPASS (3
’
b111) Allows the IC to remain in normal functional
mode and selects 1-bit bypass register between TDI and TDO.
During this instruction, serial data is transferred from TDI to
TDO without affecting operation of the IC.
INTERNAL WRITE ACCESS
Up to 20 bits of data (as needed) can be written by the process
described below. Any high order bytes that are needed are writ-
ten to the corresponding data registers defined in the external
3-bit address space. The least significant byte is then written to
DR0 at address (000). When a write to DR0 is detected, the
internal microprocessor port state machine then moves the data
in DR2-DR0 to the internal address pointed to by the address in
the LAR and AMR.
Write Pseudocode
void write_micro(ext_address, int data);
main();
{
/
*
This code shows the programming of the NCO phase offset
register using the write_micro function as defined above. The
variable address is the External Address A[2:0] and data is the
value to be placed in the external interface register.
Internal Address = 0x087
*
/
// holding registers for NCO phase byte wide access data
int d1, d0;
// NCO frequency word (16-bits wide)
NCO_PHASE = 0xCBEF;
// write ACR
write_micro(7, 0x03);
// write CAR
write_micro(6, 0x03);
// write DR1 with D[15:8]
d1 = (NCO_PHASE & 0xFF00) >> 8;
write_micro(1, d1);
// write DR0 with D[7:0]
// On this write all data is transferred to the internal address
d0 = NCO_FREQ & 0xFF;
write_micro(0, d0);
} // end of main
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相关代理商/技术参数 |
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|---|---|
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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