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参数资料
| 型号： | AD6624AABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | PLASTIC, BGA-196 |
| 文件页数： | 32/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624AABC |
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REV. 0
AD6624A
–32–
register which allows decimation up to 256, for most filtering
scenarios, the decimation should be limited to values between
1 and 32. Higher decimations are allowed, but the alias protection
of the RCF may not be acceptable for some applications.
0xA1: RCF Decimation Phase (P
RCF
)
This register allows any one of the M
RCF
phases of the filter to
be used and can be adjusted dynamically. Each time a filter is
started, this phase is updated. When a channel is synchronized,
it will retain the phase setting chosen here. This can be used as
part of a timing recovery loop with an external processor or can
allow multiple RCFs to work together while using a single RCF
pair. The RCF section of the data sheet should be consulted for
further details.
0xA2: RCF Number of Taps Minus One (N
RCF
–1)
The number of taps for the RCF filter minus one is written here.
0xA3: RCF Coefficient Offset (CO
RCF
)
This register is used to specify which section of the 256-word
coefficient memory is used for a filter. It can be used to select
among multiple filters that are loaded into memory and referenced
by this pointer. This register is shadowed and the filter pointer is
updated every time a new filter is started. This allows the Coef-
ficient Offset to be written even while a filter is being computed
with disturbing operation. The next sample that comes out of
the RCF will be with the new filter.
0xA4: RCF Control Register
The RCF Control Register is an 11-bit register that controls
general features of the RCF as well as output formatting. The
bits of this register and their functions are described below.
Bit 10
bypasses the RCF filter and sends the CIC5 output data
to the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5
data can be accessed from this register if Bit 9 of the Serial
Control Register at channel address 0xA9 is set.
Bit 9
of this register controls the source of the input data to the
RCF. If this bit is 0, the RCF processes the output data of its
own channel. If this bit is 1, it processes the data from the CIC5
of another channel. The CIC5 that the RCF is connected to
when this bit is 1 is shown in the table below. This can be used
to allow multiple RCFs to be used together to process wider
bandwidth channels. See the Multiprocessing section of the data
sheet for further details.
Table IX. RCF Input Configurations
Channel
RCF Input Source when Bit 9 is 1
0
1
2
3
1
0
1
1
Bit 8
is used as an extra address to allow a second block of 128
words of CMEM to be addressed by the channel addresses at
0x00
–
0x7F. If this bit is 0, the first 128 words are written and if
this bit is 1, a second 128 words is written. This bit is only used
to program the Coefficient Memory. It is not used in any way by
the processing and filters longer than 128 taps can be performed.
Bit 7
is used to help control the output formatting of the AD6624
’
s
RCF data. This bit is only used when the 8 + 4 or 12 + 4 floating-
point modes are chosen. These modes are enabled by Bits 5 and
4 of this register below. When this bit is 0, the I and Q output
exponents are determined separately based on their individual
magnitudes. When this bit is 1, the I and Q data is a complex
floating-point number where I and Q use a single exponent that
is determined based on the maximum magnitude of I or Q.
Bit 6
is used to force the Output Scale Factor in Bits 3
–
0 of this
register to be used to scale the data even when one of the Floating
Point Output modes is used. If the number is too large to represent
with the Output Scale chosen, the mantissas of the I and Q data
clip and do not overflow.
Bits 5 and 4
choose the output formatting option used by the RCF
data. The options are defined in Table X and are discussed further
in the Output Format section of the data sheet.
Table X. Output Formats
Bit Values
Output Option
1x
01
00
12-Bit Mantissa and 4-Bit Exponent (12 + 4)
8-Bit Mantissa and 4-Bit Exponent (8 + 4)
Fixed-Point Mode
Bits 3
–
0
of this register represent the Output Scale Factor of the
RCF. They are used to scale the data when the output format is
in fixed-point mode or when the Force Exponent bit is high.
0xA5: BIST Register for I
This register serves two purposes. The first is to allow the complete
functionality of the I data path in the channel to be tested in the
system. The BIST section of the data sheet should be consulted for
further details. The second function is to provide access to the I
output data through the microport. To accomplish this, the Map
RCF data to BIST bit in the Serial Port Control register, 0xA9,
should be set high. Sixteen-bits of I data can then be read through
the microport in either the 8 + 4, 12 + 4, 12-bit linear or 16-bit
linear output modes. This data may come from either the
formatted RCF output or the CIC5 output.
0xA6: BIST Register for Q
This register serves two purposes. The first is to allow the complete
functionality of Q data path in the channel to be tested in the
system. The BIST section of the data sheet should be consulted for
further details. The second function is to provide access to the
Q output data through the microport. To accomplish this, the Map
RCF data to BIST bit in the Serial Port Control register, 0xA9,
should be set high. Sixteen bits of Q data can then be read through
the microport in either the 8 + 4, 12 + 4, 12-bit linear or 16-bit
linear output modes. This data may come from either the
formatted RCF output or the CIC5 output.
0xA7: BIST Control Register
This register controls the number of outputs of the RCF or CIC
filter that are observed when a BIST test is performed. The BIST
signature registers at addresses 0xA5 and 0xA6 will observe this
number of outputs and then terminate. The loading of these regis-
ters also starts the BIST engine running. Details of how to utilize
the BIST circuitry are defined in the BIST section of the data sheet.
0xA8: RAM BIST Control Register
This register is used to test the memories of the AD6624A should
they ever be suspected of a failure. Bit 0 of this register is written
with a one when the channel is in SLEEP and the user waits for
1600 CLKs and then polls the bits. If Bit 1 is high, the CMEM
failed the test and if Bit 2 is high, the data memory used by the
RCF failed the test.
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相关代理商/技术参数 |
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|---|---|
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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