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参数资料
| 型号： | AD6624AABC |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA196 |
| 封装： | PLASTIC, BGA-196 |
| 文件页数： | 23/40页 |
| 文件大小： | 636K |
| 代理商： | AD6624AABC |
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REV. 0
AD6624A
–23–
MICRO
REGISTER
I0
I31
Q0
Q31
SHADOW
REGISTER
I0
I31
Q0
Q31
NCO
FREQUENCY
REGISTER
I0
I31
Q0
Q31
FROM MICROPORT
NCO FREQUENCY
UPDATE HOLD-OFF
COUNTER
B0
B15
TC
AD6624 CLK
SOFT SYNC ENABLE
PIN SYNC ENABLE
TO
NCO
ENB
Figure 28. NCO Shadow Register and Hold-Off Counter
Start
Start refers to the start-up of an individual channel, chip, or
multiple chips. If a channel is not used, it should be put in the
Sleep mode to reduce power dissipation. Following a hard reset
(low pulse on the AD6624A
RESET
pin), all channels are placed
in the Sleep mode. Channels may also be manually put to sleep
by writing to the mode register controlling the sleep function.
Start with No Sync
If no synchronization is needed to start multiple channels or
multiple AD6624s, the following method should be used to
initialize the device.
1. To program a channel, it should first be set to Sleep mode
(bit high) (Ext Address 3). All appropriate control and memory
registers (filter) are then loaded. The Start Update Hold-Off
Counter (0x83) should be set to 1.
2. Set the appropriate Sleep bit low (Ext Address 3). This enables
the channel. The channel must have Sleep mode low to activate
a channel.
Start with Soft Sync
The AD6624A includes the ability to synchronize channels or
chips under microprocessor control. One action to synchronize
is the start of channels or chips. The Start Update Hold-Off
Counter (0x83), in conjunction with the Start bit and Sync bit
(Ext Address 5), allows this synchronization. Basically, the Start
Update Hold-Off Counter delays the Start of a channel(s) by its
value (number of AD6624A CLKs). The following method is
used to synchronize the start of multiple channels via micro-
processor control.
1. Set the appropriate channels to Sleep mode (a hard reset
to the AD6624A Reset pin brings all four channels up in
Sleep mode).
2. Note that the time RDY (Pin 57) goes high to when the NCO
begins processing data is the contents of the Start Update
Hold-Off Counter(s) (0x83) plus six master clock cycles.
3. Write the Start Update Hold-Off Counter(s) (0x83) to the
appropriate value (greater than 1 and less than 2
16
–
1
). If the
chip(s) is not initialized, all other registers should be loaded
at this step.
4. Write the Start bit and the Sync bit high (Ext Address 5).
5. This starts the Start Update Hold-Off Counter counting
down. The counter is clocked with the AD6624A CLK signal.
When it reaches a count of one, the Sleep bit of the appropri-
ate channel(s) is set low to activate the channel(s).
Start with Pin Sync
The AD6624A has four Sync pins, A, B, C, and D, that can
be used to provide for very accurate synchronization channels.
Each channel can be programmed to look at any of the four sync
pins. Additionally, any or all channels can monitor a single Sync
pin or each can monitor a separate pin, providing complete flexibil-
ity of synchronization. Synchronization of Start with one of the
external signals is accomplished with the following method.
1. Set the appropriate channels to Sleep mode (a hard reset
to the AD6624A
RESET
pin brings all four channels up in
Sleep mode).
2. Note that the time from when the SYNC pin goes high to
when the NCO begins processing data is the contents of the
Start Update Hold-Off Counter(s) (0x83) plus three master
clock cycles.
3. Write the Start Update Hold-Off Counter(s) (0x83) to the
appropriate value (greater than 1 and less than 2
16
–
1
). If the
chip(s) is not initialized, all other registers should be loaded
at this step.
4. Set the Start on Pin Sync bit and the appropriate Sync Pin
Enable high (Ext Address 4 ) (A, B, C, or D).
5. When the Sync pin is sampled high by the AD6624A CLK,
it enables the count-down of the Start Update Hold-Off
Counter. The counter is clocked with the AD6624A CLK
signal. When it reaches a count of one, the Sleep bit of the
appropriate channel(s) is set low to activate the channel(s).
Hop
Hop is a jump from one NCO frequency to a new NCO frequency.
This change in frequency can be synchronized via microprocessor
control (Soft Sync) or an external Sync signal (Pin Sync) as
described below.
To set the NCO frequency without synchronization the following
method should be used.
Set Freq No Hop
1. Set the NCO Freq Hold-Off counter to 0.
2. Load the appropriate NCO frequency. The new frequency
will be immediately loaded to the NCO.
Hop with Soft Sync
The AD6624A includes the ability to synchronize a change in
NCO frequency of multiple channels or chips under micropro-
cessor control. The NCO Freq Hold-Off counter (0x84), in
conjunction with the Hop bit and the Sync bit (Ext Address 4),
allow this synchronization. Basically, the NCO Freq Hold-Off
counter delays the new frequency from being loaded into the
NCO by its value (number of AD6624A CLKs). The following
method is used to synchronize a hop in frequency of multiple
channels via microprocessor control.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD6624AS | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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