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参数资料
| 型号： | AD6624AS |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封装： | PLASTIC, MQFP-128 |
| 文件页数： | 28/40页 |
| 文件大小： | 506K |
| 代理商： | AD6624AS |
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REV. B
AD6624
–28–
Table VIII. Channel Address Memory Map (continued)
Ch Address
Register
Bit Width
Comments
A5
A6
A7
A8
BIST Signature for I Path
BIST Signature for Q Path
# of BIST Outputs to Accumulate
RAM BIST Control Register
16
16
20
3
BIST-I
BIST-Q
19–0: # of Outputs (Counter Value Read)
2:
D-RAM Fail/Pass
1:
C-RAM Fail/Pass
0:
RAM BIST Enable
9:
Map RCF Data to BIST Registers
8–7:
I_SDFS Control
1x:
Separate I and Q SDFS Pulses
01:
SDFS High for Entire Frame
00:
Single SDFS Pulse
6–5:
SOWL
1x:
24-Bit Words
01:
16-Bit Words
00:
12-Bit Words
4:
SBMx
3–0:
SDIVx[3:0]
A9
Serial Port Control Register
10
SCLK
SDI
DATA
t
SSI
t
HSI
Figure 39. Serial Input Data Timing Requirements
SCLK
SDO
I
15
I
14
t
DSDO
I
13
Figure 40. Serial Output Data Switching Characteristics
SCLK
SDFS
t
SSF
t
HSF
Figure 41. SDFS Timing Requirements (SBM = 0)
SDO
I
MSB
SDFS
SCLK
t
DSO
I
MSB1
SDFS MINIMUM
WIDTH IS ONE SCLK
FIRST DATA IS AVAILABLE THE FIRST
RISING SCLK AFTER SDFS GOES HIGH
Figure 42. Timing for Serial Output Port (SBM = 1)
SCLK
SDFS
SDFE
t
DSDFS
t
DSDFE
Figure 43. Serial Frame Switching Characteristics (SBM = 1)
SCLK
SDO
SDFE
t
DSDO
t
DSDFE
Q
1
Q
0
I
14
I
15
Figure 44. SDO, SDFE Switching Characteristics
SBM0
SBM0 is the Serial Bus Master pin for the Channel 0 Serial Port
only. Serial Ports 1, 2, and 3 will always default to Serial Slave
mode but can be programmed as masters in the internal register
space. The SBM0 pin gives the user the option to boot the
AD6624 through Serial Port 0 as a master. When SBM0 is high
(master mode), the AD6624 generates SCLK0 and SDFS0.
When SBM0 is low (slave mode), the AD6624 accepts external
SCLK0 and SDFS0 signals. When configured as a bus master,
the SCLK0 signal can be used to strobe data into the DSP inter-
face. When used with another AD6624 in Serial Cascade mode,
SCLK0 can be taken from the master AD6624 and used to shift
data out from the cascaded device. In this situation, SDFS of
the slave AD6624 channel is connected to the SDFE pin of the
master AD6624 channel (or the preceding chip in the chain).
When an AD6624 is in Serial Slave mode, all of the serial port
activities are controlled by the external signals SCLK and SDFS.
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| AD6624A | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6630AR-REEL | Differential, Low Noise IF Gain Block with Output Clamping |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6624AS/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD662AQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
| AD662BQ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
| AD662JN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:12-Bit Digital-to-Analog Converter |
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