参数资料
型号: AD7192BRUZ-REEL
厂商: Analog Devices Inc
文件页数: 1/41页
文件大小: 0K
描述: IC ADC 24BIT 2CH SD 24-TSSOP
设计资源: Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119)
标准包装: 2,500
位数: 24
采样率(每秒): 4.8k
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
电压电源: 模拟和数字
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 24-TSSOP
包装: 带卷 (TR)
输入数目和类型: 2 个差分,单极;2 个差分,双极;4 个伪差分,单极;4 个伪差分,双极
4.8 kHz, Ultralow Noise, 24-Bit
Sigma-Delta ADC with PGA
AD7192
Rev. A
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
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Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
FEATURES
RMS noise: 11 nV @ 4.7 Hz (gain = 128)
15.5 noise-free bits @ 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: 5 nV/°C
Gain drift: 1 ppm/°C
Specified drift over time
2 differential/4 pseudo differential input channels
Automatic channel sequencer
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AVDD: 3 V to 5.25 V
DVDD: 2.7 V to 5.25 V
Current: 4.35 mA
Temperature range: –40°C to +105°C
Package: 24-lead TSSOP
INTERFACE
3-wire serial
SPI, QSPI, MICROWIRE, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
Weigh scales
Strain gage transducers
Pressure measurement
Temperature measurement
Chromatography
PLC/DCS analog input modules
Data acquisition
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7192 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can be interfaced directly to the ADC.
The device can be configured to have two differential inputs or
four pseudo differential inputs. The on-chip channel sequencer
allows several channels to be enabled, and the AD7192 sequentially
converts on each enabled channel. This simplifies communication
with the part. The on-chip 4.92 MHz clock can be used as the
clock source to the ADC or, alternatively, an external clock or
crystal can be used. The output data rate from the part can be
varied from 4.7 Hz to 4.8 kHz.
The device has two digital filter options. The choice of filter
affects the rms noise/noise-free resolution at the programmed
output data rate, the settling time, and the 50 Hz/60 Hz
rejection. For applications that require all conversions to be
settled, the AD7192 includes a zero latency feature.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.35 mA. It is housed in a 24-lead TSSOP
package.
FUNCTIONAL BLOCK DIAGRAM
MCLK1 MCLK2
P0/REFIN2(–) P1/REFIN2(+)
DVDD DGND REFIN1(+) REFIN1(–)
AIN1
AIN2
AIN3
AIN4
AINCOM
BPDSW
AGND
AD7192
REFERENCE
DETECT
SERIAL
INTERFACE
AND
CONTROL
LOGIC
TEMP
SENSOR
CLOCK
CIRCUITRY
AVDD
AGND
DOUT/RDY
DIN
SCLK
CS
SYNC
P3
P2
AVDD
AGND
Σ-Δ
ADC
PGA
MUX
07
82
2-
0
01
Figure 1.
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