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| 型号： | AD7192BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极；4 个伪差分，单极；4 个伪差分，双极 |
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AD7192
Rev. A | Page 20 of 40
Table 17. Mode Register Bit Designations
Bit Location
Bit Name
Description
MR23 to MR21
MD2 to MD0
Mode select bits. These bits select the operating mode of the AD7192 (see Table 18).
MR20
DAT_STA
This bit enables the transmission of status register contents after each data register read. When
DAT_STA is set, the contents of the status register are transmitted along with each data register read.
This function is useful when several channels are selected because the status register identifies the
channel to which the data register value corresponds.
MR19, MR18
CLK1, CLK0
These bits are used to select the clock source for the AD7192. Either the on-chip 4.92 MHz clock or an
external clock can be used. The ability to use an external clock allows several AD7192 devices to be
synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the
AD7192.
CLK1
CLK0
ADC Clock Source
0
External crystal. The external crystal is connected from MCLK1 to MCLK2.
0
1
External clock. The external clock is applied to the MCLK2 pin.
1
0
Internal 4.92 MHz clock. Pin MCLK2 is tristated.
1
Internal 4.92 MHz clock. The internal clock is available on MCLK2.
MR17, MR16
0
These bits must be programmed with a Logic 0 for correct operation.
MR15
SINC3
Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set,
the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time.
For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a
settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no
missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4
filter gives better performance than the sinc3 filter for rms noise and no missing codes.
MR14
0
This bit must be programmed with a Logic 0 for correct operation.
MR13
ENPAR
Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit
in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the
contents of the status register are transmitted along with the data for each data register read.
MR12
CLK_DIV
Clock Divide by 2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, this
bit should be set to 0. When performing internal full-scale calibrations, this bit must be set when AVDD
is less than 4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data
rate is used while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not
compulsory to set the CLK_DIV bit when performing internal full-scale calibrations.
MR11
SINGLE
Single cycle conversion enable bit. When this bit is set, the AD7192 settles in one conversion cycle so
that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected.
MR10
REJ60
This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
MR9 to MR0
FS9 to FS0
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise (and, therefore, the effective
resolution) of the device (see Table 6 through Table 13). When chop is disabled and continuous
conversion mode is selected,
Output Data Rate = (MCLK/1024)/FS
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data
rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data
rate when converting on a single channel. When chop is enabled,
Output Data Rate = (MCLK/1024)/(N x FS)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and
MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate
from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency
is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output
data rate/2).
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