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参数资料
| 型号： | AD7192BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极；4 个伪差分，单极；4 个伪差分，双极 |
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AD7192
Rev. A | Page 36 of 40
4.75 V, the gain error post internal full-scale calibration is
0.005%, typically.
When AVDD is less than 4.75 V, the CLK_DIV bit must be set
when performing internal full-scale calibrations. The accuracy
of the internal full-scale calibration is further increased if chop
is enabled and a low output data rate is used while performing
the calibration.
A system full-scale calibration reduces the gain error to the
order of the noise irrespective of the analog power supply
voltage.
The AD7192 gives the user access to the on-chip calibration
registers, allowing the microprocessor to read the calibration
coefficients of the device and also to write its own calibration
coefficients from prestored values in the EEPROM. A read of
the registers can be performed at any time. However, the ADC
must be placed in power-down or idle mode when writing to
the registers. The values in the calibration registers are 24 bits
wide. The span and offset of the part can also be manipulated
using the registers.
GROUNDING AND LAYOUT
Because the analog inputs and reference inputs are differential,
most of the voltages in the analog modulator are common-
mode voltages. The high common-mode rejection of the part
removes common-mode noise on these inputs. The analog and
digital supplies to the AD7192 are independent and separately
pinned out to minimize coupling between the analog and
digital sections of the device. The digital filter provides
rejection of broadband noise on the power supplies, except at
integer multiples of the modulator sampling frequency.
Connect an R-C filter to each analog input pin to provide
rejection at the modulator sampling frequency. A 100 Ω
resistor in series with each analog input, a 0.1 μF capacitor
between the analog input pins, and a 0.01 μF capacitor from
each analog input to AGND are advised.
The digital filter also removes noise from the analog and
reference inputs provided that these noise sources do not
saturate the analog modulator. As a result, the AD7192 is
more immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD7192 is so high and the noise levels from the converter so
low, care must be taken with regard to grounding and layout.
The printed circuit board (PCB) that houses the ADC must be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes because it
gives the best shielding.
Although the AD7192 has separate pins for analog and digital
ground, the AGND and DGND pins are tied together internally
via the substrate. Therefore, the user must not tie these two
pins to separate ground planes unless the ground planes are
connected together near the AD7192.
In systems in which the AGND and DGND are connected
somewhere else in the system (that is, the power supply of the
system), they should not be connected again at the AD7192
because a ground loop results. In these situations, it is
recommended that the ground pins of the AD7192 be tied to
the AGND plane.
In any layout, the user must keep in mind the flow of currents
in the system, ensuring that the paths for all currents are as close as
possible to the paths the currents took to reach their destinations.
Avoid forcing digital currents to flow through the AGND.
Avoid running digital lines under the device, because this
couples noise onto the die, and allow the analog ground plane
to run under the AD7192 to prevent noise coupling. The power
supply lines to the AD7192 must use as wide a trace as possible
to provide low impedance paths and reduce the effects of
glitches on the power supply line. Shield fast switching signals
like clocks with digital ground to prevent radiating noise to
other sections of the board, and never run clock signals near the
analog inputs. Avoid crossover of digital and analog signals.
Run traces on opposite sides of the board at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
whereas signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. Decouple all analog supplies with 10 μF tantalum
capacitors in parallel with 0.1 μF capacitors to AGND. To
achieve the best results from these decoupling components,
place them as close as possible to the device, ideally right up
against the device. Decouple all logic chips with 0.1 μF ceramic
capacitors to DGND. In systems in which a common supply
voltage is used to drive both the AVDD and DVDD of the
AD7192, it is recommended that the system AVDD supply be
used. For this supply, place the recommended analog supply
decoupling capacitors between the AVDD pin of the AD7192
and AGND and the recommended digital supply decoupling
capacitor between the DVDD pin of the AD7192 and DGND.
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