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| 型号： | AD7192BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH SD 24-TSSOP |
| 设计资源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 标准包装： | 2,500 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极；4 个伪差分，单极；4 个伪差分，双极 |
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AD7192
Rev. A | Page 27 of 40
50 Hz/60 Hz Rejection
Normal mode rejection is one of the main functions of the
digital filter. With chop disabled, 50 Hz rejection is obtained
when the output data rate is set to 50 Hz, and 60 Hz rejection is
achieved when the output data rate is set to 60 Hz. Simulta-
neous 50 Hz and 60 Hz rejection is obtained when the output
data rate is set to 10 Hz. Simultaneous 50 Hz/60 Hz rejection
can also be achieved using the REJ60 bit in the mode register.
When the output data rate is programmed to 50 Hz and the
REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz.
sinc4 filter and sinc3 filter, respectively, when the output data
rate is programmed to 50 Hz and REJ60 is set to 1.
0
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–90
–100
0
255075
100
125
150
FI
LT
E
R
G
A
IN
(
dB
)
FREQUENCY (Hz)
07
82
2-
0
17
Figure 23. Sinc4 Filter Response (50 Hz Output Data Rate, REJ60=1)
0
–10
–20
–30
–40
–50
–60
–70
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–90
–100
0
255075
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FI
LT
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G
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(
dB
)
FREQUENCY (Hz)
07
82
2-
0
18
Figure 24. Sinc3 Filter Response (50 Hz Output Data Rate, REJ60=1)
Again, the sinc4 filter provides better 50 Hz/60 Hz rejection
than the sinc3 filter. Also, better stop-band attenuation is
achieved with the sinc4 filter.
When chop is enabled, lower output data rates must be used to
achieve 50 Hz and 60 Hz rejection. With REJ60 set to 1, an output
data rate of 12.5 Hz gives simultaneous 50 Hz/60 Hz rejection
when the sinc4 filter is selected, whereas an output data rate of
16.7 Hz gives simultaneous 50 Hz/60 Hz rejection when the sinc3
both output data rates when REJ60 is set to 1.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
255075
100
125
150
F
IL
T
E
R
GA
IN
(
d
B
)
FREQUENCY (Hz)
07
82
2-
1
25
Figure 25. Sinc4 Filter Response (12.5 Hz Output Data Rate,
Chop Enabled, REJ60 = 1)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
255075
100
125
150
FI
LT
E
R
G
A
IN
(
dB
)
FREQUENCY (Hz)
07
82
2-
1
26
Figure 26. Sinc3 Filter Response (16.7 Hz Output Data Rate,
Chop Enabled, REJ60 = 1)
Zero Latency
Zero latency is enabled by setting the SINGLE bit in the mode
register to 1. With zero latency, the complete settling time is
allowed for each conversion. Therefore,
fADC = 1/tSETTLE
Zero latency means that the output data rate is constant
irrespective of the number of analog input channels enabled;
the user does not need to consider the effects of channel
changes on the output data rate. The disadvantages of zero
latency are the increased noise for a given output data rate
compared with the nonzero latency mode. For example, when
zero latency is not enabled, the AD7192 has a noise-free
resolution of 18.5 bits when the output data rate is 50 Hz and
the gain is set to 128. When zero latency is enabled, the ADC
has a resolution of 17.5 bits peak-to-peak when the output data
rate is 50 Hz. The filter response also changes. Figure 19 shows
the filter response for the sinc4 filter when the output data rate
is 50 Hz (zero latency disabled). Figure 27 shows the filter
response when zero latency is enabled and the output data rate
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