参数资料
| 型号： | AD7193BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/57页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SPI 4.8KHZ 32LFCSP |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个差分，单极；4 个差分，双极；8 个伪差分，单极；8 个伪差分，双极 |
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AD7193
Data Sheet
Rev. D | Page 34 of 56
In continuous conversion mode, the ADC selects each of the
enabled channels in sequence and performs a conversion on the
channel. The DOUT/RDY pin indicates when a valid conversion is
available on each channel. When several channels are enabled,
the contents of the status register should be attached to the 24-bit
word allowing the user to identify the channel that corresponds
to each conversion. The four LSBs of the status register indicate
the channel to which the conversion corresponds. Table 23 and
Table 24 show the channel options for differential mode and
pseudo differential mode with the corresponding channel ID
values in the status register. To attach the status register value
to the conversion, Bit DAT_STA in the mode register should
be set to 1.
When several channels are enabled, the ADC allows the complete
filter settling time to generate a valid conversion each time the
channel is changed. The AD7193 automatically takes care of this
through the following sequence:
1. When a channel is selected, the modulator and filter are
reset.
2. The AD7193 allows the complete settling time to generate
a valid conversion.
3. DOUT/RDY indicates when a valid conversion is available.
4. The AD7193 selects the next enabled channel and converts
on that channel.
5. The user can read the data register while the ADC is
performing the conversion on the next channel.
The time required to read a valid conversion from all enabled
channels is equal to
tSETTLE × Number of Enabled Channels
For example, if the sinc4 filter is selected, chop is disabled, and
zero latency is disabled, the settling time for each channel equals
tSETTLE = 4/fADC
where fADC is the output data rate when continuously converting
on a single channel.
Therefore, the time required to read all enabled channels is
(4× Number of Enabled Channels)/fADC
RDY
CONVERSIONS
CHANNEL A
CHANNEL B
1/fADC
CHANNEL C
08367-
060
Figure 24. Channel Sequencer
DIGITAL INTERFACE
As indicated in the On-Chip Registers section, the programmable
functions of the AD7193 are controlled using a set of on-chip
registers. Data is written to these registers via the serial interface
of the part. Read access to the on-chip registers is also provided
by this interface.
All communication with the part must start with a write to the
communications register. After power-on or reset, the device
expects a write to its communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation, and it determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part begins with a
write operation to the communications register, followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register, followed by a read
operation from the selected register.
The serial interface of the AD7193 consists of four signals: CS,
DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer
data into the on-chip registers and DOUT/RDY is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
or DOUT/RDY) occur with respect to the SCLK signal.
The DOUT/RDY pin also functions as a data-ready signal, the
line going low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the data register to indicate when not to read from the device,
to ensure that a data read is not attempted while the register is
being updated. CS is used to select a device. It can be used to
decode the AD7193 in systems where several components are
connected to the serial bus.
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7193 using CS to decode the part. Figure 3 shows the
timing for a read operation from the output shift register of the
AD7193, and Figure 4 shows the timing for a write operation to
the input shift register. It is possible to read the same word from
the data register several times even though the DOUT/RDY line
returns high after the first read operation. However, care must
be taken to ensure that the read operations are completed before
the next output update occurs. In continuous read mode, the
data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7193. The end of the conversion can
be monitored using the RDY bit or pin. This scheme is suitable
for interfacing to microcontrollers. If CS is required as a decoding
signal, it can be generated from a port pin. For microcontroller
interfaces, it is recommended that SCLK idle high between data
transfers.
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| AD7193BCPZ-RL | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
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| AD7193BRUZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 4.8KHZ TSSOP-28 |
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