参数资料
| 型号： | AD7193BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/57页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SPI 4.8KHZ 32LFCSP |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 托盘 |
| 输入数目和类型： | 4 个差分，单极；4 个差分，双极；8 个伪差分，单极；8 个伪差分，双极 |
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Data Sheet
AD7193
Rev. D | Page 43 of 56
Simultaneous 50 Hz/60 Hz rejection can also be achieved using
the REJ60 bit in the mode register. When FS[9:0] is set to 96
and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz.
The output data rate is 50 Hz when zero latency is disabled and
12.5 Hz when zero latency is enabled. Figure 35 shows the
frequency response of the sinc4 filter. The filter provides 50 Hz
± 1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum,
assuming a stable 4.92 MHz master clock.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
FREQUENCY (Hz)
F
IL
T
E
R
GA
IN
(
d
B
)
08
36
7
-03
1
Figure 35. Sinc4 Filter Response (FS[9:0] = 96, REJ60 = 1)
SINC3 FILTER (CHOP DISABLED)
A sinc3 filter can be used instead of the sinc4 filter. The filter is
selected using the SINC3 bit in the mode register. The sinc3
filter is selected when the SINC3 bit is set to 1.
This filter has good noise performance when operating with
output data rates up to 1 kHz. It has moderate settling time and
moderate 50 Hz/60 Hz (±1 Hz) rejection.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
08
367
-03
2
Figure 36. Sinc3 Filter (Chop Disabled)
Sinc3 Output Data Rate and Settling Time
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
fADC = fCLK/(1024 × FS[9:0])
where:
fADC is the output data rate.
fCLK is the master clock (4.92 MHz nominal).
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time is equal to
tSETTLE = 3/fADC
The 3 dB frequency is equal to
f3dB = 0.272 × fADC
Table 30 gives some examples of FS settings and the corresponding
output data rates and settling times.
Table 30. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
Output Data Rate (Hz)
Settling Time (ms)
480
10
300
96
50
60
80
60
50
When a channel change occurs, the modulator and filter reset. The
complete settling time is allowed to generate the first conversion
after the channel change (see Figure 37). Subsequent conversions
on this channel are available at 1/fADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
0
83
67
-0
33
Figure 37. Sinc3 Channel Change
When conversions are performed on a single channel and a
step change occurs, the ADC does not detect the change in
analog input. Therefore, it continues to output conversions at
the programmed output data rate. However, it is at least three
conversions later before the output data accurately reflects the
analog input. If the step change occurs while the ADC is processing
a conversion, the ADC takes four conversions after the step change
to generate a fully settled result.
1/
fADC
ANALOG
INPUT
ADC
OUTPUT
FULLY
SETTLED
0
836
7-
0
34
Figure 38. Asynchronous Step Change in Analog Input
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