参数资料
| 型号： | AD7194BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/57页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT SPI 4.8K 32-LFCSP |
| 产品培训模块： | Weigh Scale Introduction |
| 标准包装： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 8 个差分，单极；8 个差分，双极；16 个伪差分，单极；16 伪差分，双极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
| 其它名称： | AD7194BRUZ AD7194BRUZ-ND |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页当前第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页
AD7194
Data Sheet
Rev. A | Page 36 of 56
RESET
The circuitry and serial interface of the AD7194 can be reset
by writing consecutive 1s to the device; 40 consecutive 1s are
required to perform the reset. This resets the logic, the digital
filter, and the analog modulator, whereas all on-chip registers
are reset to their default values.
A reset is automatically performed on power-up. When a reset is
initiated, the user must allow a period of 200 μs before acces-
sing any of the on-chip registers. A reset is useful if the serial
interface loses synchronization due to noise on the SCLK line.
SYSTEM SYNCHRONIZATION
The SYNC input allows the user to reset the modulator and the
digital filter without affecting any of the setup conditions on the
part. This allows the user to start gathering samples of the analog
input from a known point in time, that is, the rising edge of
SYNC. SYNC needs to be taken low for at least four master
clock cycles to implement the synchronization function.
If multiple AD7194 devices are operated from a common
master clock, they can be synchronized so that their data
registers are updated simultaneously. A falling edge on the
SYNC pin resets the digital filter and the analog modulator and
places the AD7194 into a consistent, known state. While the
SYNC pin is low, the AD7194 is maintained in this state. On the
SYNC rising edge, the modulator and filter are taken out of this
reset state and, on the next clock edge, the part starts to gather
input samples again. In a system using multiple AD7194 devices,
a common signal to their SYNC pins synchronizes their opera-
tion. This is normally done after each AD7194 has performed
its own calibration or has calibration coefficients loaded into its
calibration registers. The conversions from the AD7194s are
then synchronized.
The part is taken out of reset on the master clock falling edge
following the SYNC low to high transition. Therefore, when
multiple devices are being synchronized, the SYNC pin should
be taken high on the master clock rising edge to ensure that all
devices begin sampling on the master clock falling edge. If the
SYNC pin is not taken high in sufficient time, it is possible to
have a difference of one master clock cycle between the devices;
that is, the instant at which conversions are available differs
from part to part by a maximum of one master clock cycle.
The SYNC pin can also be used as a start conversion command.
In this mode, the rising edge of SYNC starts conversion, and the
falling edge of RDY indicates when the conversion is complete.
The settling time of the filter has to be allowed for each data
register update. For example, if the ADC is configured to use
the sinc4 filter, zero latency is disabled, and chop is disabled, the
settling time equals 4/fADC where fADC is the output data rate
when continuously converting on a single channel.
ENABLE PARITY
When the ENPAR bit in the mode register is set to 1, parity is
enabled. The contents of the status register must be transmitted
along with each 24-bit conversion when the parity function is
enabled. To append the contents of the status register to each
conversion read, the DAT_STA bit in the mode register should
be set to 1. For each conversion read, the parity bit in the status
register is programmed so that the overall number of 1s trans-
mitted in the 24-bit data-word is even. Therefore, for example,
if the 24-bit conversion contains 11 ones (binary format), the
parity bit is set to 1 so that the total number of ones in the serial
transmission is even. If the microprocessor receives an odd
number of 1s, it knows that the data received has been corrupted.
The parity function does not ensure that all errors are detected.
For example, two bits of corrupt data can result in the micro-
processor receiving an even number of ones. Therefore, an error
condition is not detected.
CLOCK
The AD7194 includes an internal 4.92 MHz clock on-chip. This
internal clock has a tolerance of ±4%. Either the internal clock
or an external crystal/clock can be used as the clock source to
the AD7194. The clock source is selected using the CLK1 and
CLK0 bits in the mode register. When an external crystal is
used, it must be connected across the MCLK1 and MCLK2
pins. The crystal manufacturer recommends the load capa-
citances required for the crystal. The MCLK1 and MCLK2
pins of the AD7194 have a capacitance of 15 pF, typically. If
an external clock source is used, the clock source must be
connected to the MCLK2 pin, and the MCLK1 pin can remain
floating.
The internal clock can also be made available at the MCLK2
pin. This is useful when several ADCs are used in an appli-
cation and the devices must be synchronized. The internal clock
from one device can be used as the clock source for all ADCs in
the system. Using a common clock, the devices can be synchro-
nized by applying a common reset to all devices, or the SYNC
pin can be pulsed.
TEMPERATURE SENSOR
Embedded in the AD7194 is a temperature sensor. This is
selected using the TEMP bit in the configuration register. When
the TEMP bit is set to 1, the temperature sensor is enabled.
When the temperature sensor is selected and bipolar mode is
selected, the device should return a code of 0x800000 when the
temperature is 0 Kelvin, theoretically. A one-point calibration is
needed to obtain the optimum performance from the sensor.
Therefore, a conversion at 25°C should be recorded and the
sensitivity calculated. The sensitivity is 2815 codes/°C,
approximately. The equation for the temperature sensor is
Temperature (K) = (Conversion 0x800000)/2815 K
Temperature (°C) = Temperature (K) 273
相关PDF资料 |
PDF描述 |
|---|---|
| AD7195BCPZ-RL7 | IC AFE 24BIT 4.8K 32LFSP |
| AD7225BQ | IC DAC 8BIT QUAD W/AMP 24-CDIP |
| AD7226BQ | IC DAC 8BIT QUAD W/AMP 20-CDIP |
| AD7228CQ | IC DAC 8BIT OCTAL W/AMP 24-CDIP |
| AD7233BNZ | IC DAC 12BIT SRL W/AMP 8PDIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7194BCPZ-REEL | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7194BCPZ-REEL7 | 功能描述:IC ADC 24BIT SPI 4.8KHZ 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7195 | 制造商:AD 制造商全称:Analog Devices 功能描述:4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation |
| AD7195BCPZ | 功能描述:IC AFE 24BIT 4.8K 32LFSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD7195BCPZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 4.8KSPS CSP-32 |
发布紧急采购，3分钟左右您将得到回复。